臺灣博碩士論文加值系統

移動估測在視訊編碼的過程中，具有非常高的複雜度，因此成為即時影像編碼的瓶頸，在高壓縮律規格(H.264/AVC)的可調式視訊編碼中，由於其額外引用的層間預測編碼，使得原本整數點移動估計之高頻寬存取所帶來的問題更加嚴重。因此，本論文引用一能有效改善層間預測高頻寬存取的演算法並提出相對應的硬體架構，此硬體架構使得整數點移動估測和層間預測能併行運算並共用運算時所需的資料。此外，為了改善分數點移動估測的高複雜度和高計算量，本論文引用了一分數點快速演算法並提出相對應的硬體架構，此提出之架構與先前架構相比運算速度可增加三倍。由於多種移動向量和來自於層間預測的多種編碼方式，使得分數點移動估測的運算量和運算時間大為增加，為了更進一步減少分數點移動估測的運算時間和運算量，本論文引用了一能有效篩選欲執行分數點移動估測的編碼方式之演算法，並且將其延伸與多層解析度移動估測演算法之結果一併考慮，進而提出一種能從不同層解析度編碼方式之中有效篩選欲執行分數點移動估測的編碼方式之演算法，經過此演算法，相較於原先的最多20種編碼方式，此演算法篩選至僅僅3種編碼方式須要被執行分數點移動估測，此演算法相較於先前無篩選的做法訊雜比下降了0.106dB而位元率增加了3.542%。

Motion estimation is (ME) is the most complex part and the bottle neck of a real time video encoder. The adoption of inter-layer prediction (IL prediction) in H.264/AVC SVC extension even increases the computing time and memory bandwidth of ME. Thus, we adopted the previous data efficient inter-layer prediction algorithm [4] to save the memory bandwidth. In this thesis, we propose the corresponding hardware architecture for inter-layer prediction which can process INTER mode and different inter-layer prediction modes in parallel to save the computing time and memory bandwidth. Furthermore, in order to reduce the high complexity and computation of FME, we adopt the Single-Pass Fractional Motion Estimation (SPFME) as our fast FME algorithm in our FME process. We then propose the corresponding FME hardware architecture for SPFME according to the previous architecture of FME design [3]. Compared with the previous architecture, our proposed architecture can speed up to four times faster. There are many prediction modes due to the adoption of inter-layer prediction and different block types. Thus, to further reduce the complexity and computing time of FME, we adopt the pre-selection algorithm of Li’s to eliminate some prediction modes from FME process. However, the Parallel Multi-Resolution Motion Estimation (PMRME) algorithm [1] is adopted in our IME process. Hence, we further propose a multi-level mode filtering scheme to select 3 prediction modes from 3 different search levels. Finally, we integrate the adopted IL prediction, mode filtering, and the SPFME algorithm. The simulation results shows that the proposed function flow with mode filtering can achieve average 3.542% of bit-rate increment and 0.106dB of PSNR degradation in CIF sequence for 2 spatial layers. The implementation results of the whole ME architecture is also shown. It can support CIF+480p+1080p video @60 fps under 135MHz.

Contents
Chapter 1. Introduction ................1
1.1. Overview of SVC ...................1
Chapter 2. Related work overview .......5
2.1. Parallel multi-resolution motion estimation (PMRME)[1]......................... 5
2.2. Data efficient Inter-layer prediction algorithm ......................................... 7
2.3. Fast FME algorithm- Single-pass Fractional Motion Estimation (SPFME) .. 11
Chapter 3. Mode filtering for IME ................. 14
3.1. The Matching Criteria ........................ 14
3.2. Motivation of mode filtering ......................................... 14
3.3. Efficient pre-selection algorithm for fractional motion estimation in H.264/AVC scalable video extension ......................................... 18
3.3.1. Observation and analysis ...........................................18
3.3.2. The pre-selection algorithm for inter-layer prediction .............................. 20
3.4. Proposed mode filtering algorithm for multi-level .................................. 22
3.5. Mode filtering by IBL and IBLR mode .............................................. 23
Chapter 4. Hardware architecture design .............................................26
4.1. Design Spec .................................. 26
4.2. Architecture design of IME ............................................... 28
4.2.1. Overview of PMRME architecture design ............................................ 28
4.2.2. Proposed architecture design for inter-layer prediction ........................... 34
4.2.3. Search scheduling of IME ................................................41
4.3. Architecture design of FME ................................................45
4.3.1. Overview of previous FME architecture design ......................................... 46
4.3.2. Proposed FME design ............................................ 50
4.3.2.1. Overall architecture and primary modules ........................... 50
4.3.2.2. FME luma module .......................... 52
4.3.2.3. The parallel processing architecture of interpolation unit ... 53
4.3.2.4. The skip IBL mode for FME .................................................... 55
4.4.Reference SRAMs ...................................................57
4.4.1. Level 0 and FME SRAM ................................................... 57
4.4.2. SRAMs of level 1 and level2 ..................................................58
4.5. Memory schedule ................................................60
Chapter 5. Simulation and Implementation results ............................................... 63
5.1. Simulation results .................................................63
5.2. Hardware implementation results ................................................ 68
Chapter 6. Conclusion and future work ................................................... 74
Reference .............................................. 75

[1] T. Wiegand, G. Sullivan, J. Reichel, H. Schwarz and M. Wien, ISO/IEC JTC1/SC29/WG11 and ITU-T SG16 Q.6: JVT-X201 ‘Joint Draft ITU-T Rec. H.264 | ISO/IEC 14496-10/Amd.3 Scalable video coding,’ 24th Meeting, Geneva, Switzerland, Jun.29-Jul.5, 2007.
[2] C.-C. Lin, Y.-K. Lin and T.-S. Chang, “PMRME: A parallel multi-resolution motion estimation algorithm and architecture for HDTV sized H.264 video coding,” Proceedings of IEEE International Conference on Acoustics, Speech and Signal Proceeding, vol.2, pp.II-385-II-388, April 2007.
[3] Tzu-Yun Kuo, Yu-Kun Lin, and Tian-Sheuan Chang, “SIFME: A single iteration fractional-pel motion estimation algorithm and architecture for HDTV sized H.264 video coding,” IEEE Int. Conf. Acout., Speech, Signal Process, vol. 1, pp. 1185–1188, 2007.
[4] Hsiao-Shan Huang, Gwo-Long Li, and Tian-Sheuan Chang, “Low Memory Bandwidth Prediction Method for H.264/AVC Scalable Video Extension,” Proceeding of APSIPA Annual Summit and Conference, pp. 294-298, Oct. 2009.
[5] Giwon Kim, Jaemoon Kim, Student Member, IEEE, Chong-Min Kyung, Fellow, IEEE, “A single-pass fractional motion estimation architecture for H.264 video codec,” Proceeding of IEEE International Conference on Multimedia and Expo, pp. 661-666, July 2010
[6] ISO/IEC International Standard 14496-10, Information technology – Coding of audio-visual objects – Part 10: Advanced Video Coding, third edition, Dec. 2005, corrected version, March 2006.
[7] Gwo-Long Li and Tian-Sheuan Chang, “An Efficient Mode Pre-Selection Algorithm for H.264/AVC Scalable Video Extension Fractional Motion Estimation,”
76
IEEE International Conference on Digital Signal Processing, Corfu, Greece, July 2011.
[8] C.-C. Yang, K.-J. Tan, Y.-C. Yang, and J.-I. Guo, "Low complexity fractional motion estimation with adaptive mode selection for H.264/AVC," Proceeding of IEEE International Conference on Multimedia and Expo, pp.673-678, July 2010.
[9] C.-C. Lin, Y.-K. Lin, and T.-S. Chang, "A fast algorithm and its architecture for motion estimation in MPEG-4 AVC/H.264," in Proceeding of Asia Pacific Conference on Circuits and Systems, pp.1250-1253, December 2006.
[10] H. Nisar and T.-S. Choi, "Fast and efficient fractional pixel motion estimation for H.264/AVC video coding," in Proceeding of IEEE International Conference on Image Processing, pp.1561-1564, October 2008.
[11] C.-Y. Kao, C.-L. Wu, and Y.-L. Lin, "A high-performance three-engine architecture for H.264/AVC fractional motion estimation," IEEE Transactions on Very Large Scale Integration System, vol.18, no.4, pp.662-666, April 2010
[12] Y.-J. Wang, C.-C. Cheng, and T.-S. Chang, "A fast algorithm and its VLSI architecture for fractional motion estimation for H.264/MPEG-4/AVC video coding," IEEE Transactions on Circuits and Systems for Video Technology, vol.17, no.5, pp.578–583, May 2007.
[13] Chao-Yang Kao and Youn-Long Lin, Senior Member, “A memory-efficient and highly parallel architecture for variable block Size integer motion estimation in H.264/AVC,” IEEE Very Large Scale Integration (VLSI) Systems, vol.18, issue.5, pp. 866–874, June 2010.
[14] Xianghu Ji, Chuang Zhu, Huizhu Jia, Xiaodong Xie, Haibin Yin, “A hardware-efficient architecture for multi-resolution motion estimation using fully reconfigurable processing element array,” 2011 IEEE International Conference Multimedia and Expo (ICME),pp. 1–6 , 11-15 July 2011.
[15] Z.Y. Liu, Y. Song, M. Shao, S. Li, L.F. Li, Ishiwata, S., Nakagawa, M., Goto, S., Ikenaga T., “HDTV 1080P H.264/AVC encoder chip design and performance analysis,” IEEE J. Solid-State Circuits, vol. 44, no. 2, 816 pp. 594–608, Feb. 2009. [16] Giwon Kim, Jaemoon Kim, Chong-Min Kyung, “A low cost single-pass fractional motion estimation architecture using bit clipping for H.264 video codec,” 2010 IEEE International Conference Multimedia and Expo (ICME), pp. 661–666, 19-23 July 2010 [17] Nam Thang Ta, Jim Rim Choi, Jae Hoon Kim, Seon Cheol Hwang, Shi Hye Kim, “Fully parallel fractional motion estimation for H.264/AVC encoder,” 2009 Intelligent Computing and Intelligent Systems (ICIS) conference, vol. 4, pp. 306–309, 20-22 Nov. 2009