臺灣博碩士論文加值系統

記憶體模組在現代電腦裡為一項不可缺少的產品；工作頻率更快以及體積的迷你化更是現代人所追求的。為了達到這些目標，記憶體模組內部晶片連線與電源系統之電磁效應影響在電腦設計時也相對地需要被審慎考慮。
本篇論文主要分為兩個部分，第一部分首先針對記憶體模組內不同工作區塊，指令/位址線(command/address line)與資料線(data line)，建立了單端信號線傳輸路徑上各個不連續結構的等效電路模型並將其串連起來，透過此分段化之模型，可了解各段不連續結構對於信號完整度的影響，同時利用實驗量測來驗證此模型的準確性。藉由建立電源和信號完整度的共同模擬環境，並整合了主動電路元件模型，也可瞭解到電源雜訊的影響。此方法也可應用在建立差模信號時序線的等效模型上，以此分析時序信號之信號完整度對取樣時間的影響。
第二部分則針對印刷電路板(PCB)上之非理想效應與構裝(package)結構作補償設計。PCB 上之非理想效應又主要可分三項：第一項為接地雜訊對信號連通柱造成的電感特性，利用增加連通柱的電容特性作補償；第二項為使用兩段不等長的傳輸線補償PCB走線分接連通柱長度不匹配的影響；第三項為差動信號線之飛越式(fly-by)佈線，提供一設計圖表可迅速地得到阻抗匹配所需之尺寸參數。而對於構裝結構，首先是指令/位址線之佈線重新配置，以期得到最小的等效電感值，與信號線間的串音效應，使信號完整度更理想。再來利用資料線構裝結構的等效電感值，配合其後主動電路的負載電容與傳輸線之特性阻抗作阻抗匹配。
總結以上對於高速記憶體模組的信號分析方法與補償設計，將有助於縮短業界硬體工程師的設計時程並使記憶體模組達到更有效率的應用。

Memory module has become a essential product in modern computer systems. People are always pursuing digital products with faster operating frequency and tiny volume. For achieving this goals, there are many things that should be considered carefully in computer design, for example, the chip connector in memory modules and the electro- magnetic problems in power systems.
There are two parts in this thesis. In the first part, the equivalent models of all discontinuities along the single-ended transmission path is extracted and then linked together for different function blocks of memory module, i.e. command/address line and data line. By this divided model, the influence of each discontinuity on signal integrity can be evaluated. Also, the accuracy of each model is verified through experiments. By means of the construction of the co-simulation environment considering signal and power integrity, and also active circuit models, the ground noise issue can be discussed as well. Similarly, this method can be applied to help extract equivalent models of differential clock line. The influence of signal integrity of differential clock line on the variation of sampling time can then be analyzed.
In the second part, it is all about the compensation design for the imperfect effects on PCB and package structure. There are three kinds of imperfect effects on PCB that need to be overcome. The first one is the overall inductive behavior of signal vias, which mainly comes from the induction of ground bounce noise. It can be compensated by increasing the capacitive loading of signal vias. For the second one, unbalanced transmission lines can be used to mitigate the influence of signal vias with unmatched lengths connecting the chip inputs. For the third one, a design curve is established to provide the required dimensions of transmission line for impedance matching design of differential fly-by layout. As for the package layout, smaller effective inductance and less crosstalk effect can be achieved through the reassignment of power/ground pins among all signal pins.
With the above signal analysis methodology and compensation designs for high- speed memory module, it can help the engineers shorten the design process and make applications for memory module more efficiently.

致　　謝 ii
摘　　要 iv
Abstract v
目　　錄 vi
圖表目錄 viii
第一章 研究動機與簡介 1
1-1 研究動機 1
1-2 文獻回顧與探討 2
1-3 章節概要 2
1-4 貢獻 3
第二章 印刷電路板之等效模型擷取與實驗驗證 5
2-1 各種信號線之完整走線介紹 6
2-2 量測環境及模擬軟體介紹 8
2-3 位址線與指令線模型擷取 9
2-4 資料線模型擷取 20
2-5 差動信號線之模型擷取 30
第三章 高速記憶體模組之完整傳輸路徑分析 35
3-1 構裝結構介紹 35
3-2 主動接收電路介紹 37
3-3 完整信號走線之模擬環境設定 38
3-4 位址線和指令線分析 40
3-5 資料線分析 47
3-6 差動信號線分析 50
第四章 印刷電路板及構裝結構之補償設計 57
4-1 穿層連通柱造成接地雜訊之補償設計 57
4-2 穿層連通柱長度不匹配之補償設計 65
4-3 差動信號線之飛躍式佈線設計 72
4-4 位址線和指令線之構裝結構佈線配置 78
第五章 結論與未來工作 87
5-1 結論 87
參考文獻 88

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