臺灣博碩士論文加值系統

在本篇論文中，主要介紹在RF領域中的低雜訊放大器，主要是利用LC-folded cascode的架構作基礎，並針對改善線性度的問題，利用二個共源級放大器的架構去實現，線性度大致可增加2 ~ 3 dB。除此之外，另外增加了一個增益控制訊號(Vtune)，調整增益控制訊號Vtune則可控制電路中的整體增益，並且不會影響到輸入端的雜訊指數及阻抗匹配。此低雜訊放大器是採用台積電CMOS0.18微米1P6M的製程而操作頻率為2.4GHz。
在低電壓工作下，可調增益低雜訊放大器包含完整的輸入阻抗和輸出阻抗匹配電路。此低雜訊放大器被設計出具有增益11.14 dB，3.981 dB雜訊指數，輸入及輸出反射損失分為-26.06 dB和-6.827 dB，1dB增益壓縮點和IIP3分為-14 dBm和-5 dBm，而此電路可以操作在1 V較低的工作電壓並且可提供10 dB的增益控制。

In the thesis, an integrated RF circuit topology that can be used to realize low voltage ( i.e. 1V ) low noise amplifier is presented. The design technique based on a narrowband LC-folded cascode topology is proposed for low voltage RF integrated circuits. Based on a LC-folded cascode LNA topology, it is implemented with a modified LC-folded cascode LNA configuration using two common source transistors to improve linearity. The linearity is improved about 2 to 3 dB. On LC-folded cascode topology, another merit that only increases in the LNA circuit complexity is an extra gain control signal, Vtune. Gain variation is achieved by controlling the Vtune, hence adjusting the overall gain of the LNA without affecting the input noise and impedance matching. The technique is applied to the design of a proposed LNA operating at 2.4 GHz using a TSMC 0.18 μm mixed signal ( 1P6M ) CMOS technology.
A low voltage, variable gain design for low noise amplifier is fully on chip between input and output. The proposed LNA chip achieves measured results of 11.14 dB for power gain, 3.981 dB for noise figure, the input and output return loss of -26.06 dB and -6.827 dB, the 1-dB compression point and IIP3 of -14 dBm and -5 dBm, respectively. The circuit has 10 dB of gain tuning, and can operate at a low supply voltage of 1 V.

Abstract……………………………………………………………vi
Contents …………………………………………………………vii
List of Figures …………………………………………………x
List of Tables …………………………………………………xiv
Chapter 1 Introduction ………………………………………1
1.1 Motivation…………………………………………………1
1.2 Design considerations for LNA…………………………2
1.3 Organization………………………………………………4
Chapter 2 RF fundamentals……………………………………5
2.1 S-parameter……………………………………………6
2.2 Gain………………………………………………………9
2.3 Noise Figure……………………………………………12
2.4 Sensitivity……………………………………………14
2.5 Linearity………………………………………………16
2.6 Stability………………………………………………22
Chapter 3 Low Noise Amplifier………………………………24
3.1 Noise model for MOSFET………………………………25
3.2 Noisy two-port networks………………………………33
3.3 Basic topologies of low noise amplifier…………37
3.4 A low voltage design technique for RF circuit…43
3.5 A linearization technique for RF circuits………47
Chapter 4 LNA Design and Realization…………………………51
4.1 LNA design…………………………………………………52
4.2 Simulation results………………………………………66
4.3 Layout………………………………………………………75
Chapter 5 Measurement Results……………………………………78
5.1 Measurement setup…………………………………………79
5.2 Measurement results………………………………………81
5.3 Summary………………………………………………………85
Chapter 6 Conclusions………………………………………………88
6.1 Discussions and summary…………………………………88
6.2 Future works………………………………………………89
References………………………………………………………………91

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