臺灣博碩士論文加值系統

本論文主要完成了一個應用於分時多工類比數位轉換器(TIADC)之時脈歪斜校正器。TIADC雖然有高取樣率的優點，但其內的子通道ADC卻有著通道不匹配問題，使得ADC的輸出效能因不匹配誤差雜訊而降低。在這些不匹配誤差中主要包含了偏移電壓誤差、增益誤差及取樣時間誤差，相較於其他誤差，取樣時間誤差在高速的應用中大大限制了ADC的效能表現，其對輸出訊號SNR的影響隨輸入訊號頻率提高而增加，因此本論為主要針對時間誤差校正演算法進行探討，依據文獻中的理論提出新的時間誤差偵測及校正電路，利用Altera Stratix III Development and Education board實現一背景式時間誤差校正器，並使用Matlab Simulink校正演算法產生的TIADC數位碼驗證校正電路的功能。此外，本篇論文中分析及量測一兩通道、90nm快閃式類比數位轉換器晶片，其輸入時脈為1.25GHz，解析度為5位元，電源電壓為1V，輸入訊號範圍640mV，正常工作時的功率消耗為55mW，輸出數位訊號經八倍下取樣後輸出以符合儀器量測速度。

This paper mainly proposes a background sampling-time skew calibrator used for timing adjustment of time-interleaved ADCs(TIADC). Though the TIADC has its merit of high-sampling rate, the mismatches between internal sub-ADCs cause mismatch errors and decrease the performance of the ADCs. These mismatch errors include offset mismatch, gain error mismatch, sampling-time error and the sampling-time error dominantly limits the performance of ADCs in high-speed applications when compared with other mismatch errors. The sampling-time error impacts the SNR of ADC outputs more seriously when the input frequency is increased. So our work mianly discuss timing calibration algorithm. We propose detection and and calibration circuits for timing errors inspired by thories of previous arts. Using ‘Altera Stratix III Development and Education board’ to fulfill the background calibrator and verifying functions of circuits by digital codes generated by Matlab Simulink model. Furthermore, this work analyzes and measures a two-chaanel, 90nm flash TIADC chip. The input clock is 1.25GHz, the resolution is 5bit, the supply voltage is 1V, the signal range is 640mV, the power consumption is 55mW under its normal operation, the digital outputs is downsampled by a factor of 8 to fit the speed requirement of used instruments.

第一章 緒論 1
1.1 研究背景 1
1.2 研究動機與目的 4
1.3 論文架構 7
第二章 分時多工類比數位轉換器簡介 8
2.1分時多工類比數位轉換器架構 8
2.2分時多工類比數位轉換器中的非理想效應 9
2.2.1偏移電壓誤差(Offset mismatch) 11
2.2.2增益誤差(Gain mismatch) 13
2.2.3取樣時間延遲誤差(Sampling-time mismatch) 16
2.2.4同時存在增益誤差、偏移電壓誤差及取樣時間延遲誤差 19
2.2.5頻寬誤差(Bandwidth mismatch) 22
2.3偏移電壓、增益、取樣延遲時間誤差對TIADC效能影響 24
2.4取樣時間誤差校正技術的發展現況 29
2.4.1 Timing Mismatch Background Calibration for Time- Interleaved ADCs 29
2.4.2 Calibration of Sample-Time Error in a Two-Channel Time-Interleaved Analog-to-Digital Converter 30
2.4.3 A 12.8 GS/s Time-Interleaved ADC With 25 GHz Effective Resolution Bandwidth and 4.6 ENOB 33
2.4.4 A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques 36
2.4.5 Comprehensive Background Calibration of Time-Interleaved Analog-to-Digital Converters 37
第三章 背景式取樣時間誤差校正理論 40
3.1多相位時脈產生器與時間延遲校正 41
3.2取樣時間誤差校正理論 44
3.2.1零點交越理論 44
3.2.2時間誤差校正器架構 48
第四章 高速類比數位轉換器使用 54
4.1兩通道分時多工快閃式類比數位轉換器設計 54
4.1.1 Constant-Vgs取樣開關設計 55
4.1.2動態比較器設計 57
4.1.3編碼器設計 59
4.1.4兩通道分時多工快閃式類比數位轉換器量測 60
4.2輸入訊號範圍2Vpp、100MS/s、十位元之AD9608量測 63
第五章 FPGA時間誤差校正器實現 66
5.1 Altera DE3現場可程式邏輯閘陣列使用 66
5.2 FPGA時間誤差校正器模擬 69
5.2.1開迴路時間誤差校正演算法 69
5.2.2高速時序交錯式類比數位轉換器資料的下取樣 72
5.2.3 Verilog校正演算法模擬 74
5.2.4 FPGA校正演算法燒錄及量測 79
5.2.5基於SOPC Builder和NIOS II的處理器合成及演算法執行 80
第六章 結果與未來展望 85
參考文獻 85

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