臺灣博碩士論文加值系統

本論文主要分為四個主題，第一個主題為利用TSMC 90nm CMOS的製程，設計應用於汽車防撞雷達W-band的低雜訊放大器(LNA)，使用共平面波導的傳輸線設計輸入與輸出阻抗匹配與佈局的走線，而此傳輸線使用ground shielding的技巧來提高Q值以減少訊號傳輸時對於基底的損耗。本章節有探討如何選擇電晶體的尺寸以及偏壓點，利用noise模型推導出較低雜訊指數的電晶體尺寸與被動元件。而實際量測後，操作頻率78GHz的輸入與輸出阻抗匹配皆有在-10dB以下，增益為12.57dB，3dB頻寬為74GHz-90GHz，IIPᴣ為-8.1dBm，雜訊指數為6.07dB，與相同頻帶的先前文獻比較，本篇論文的雜訊指數算是較低的，而量測之功率消耗為28.56mW。
第二個主題是利用TSMC 0.18µm CMOS的製程，設計應用於24GHz的接收器，利用三級的疊接架構LNA提高增益，並利用主動Balun將訊號單轉雙，混頻器使用雙端平衡式混頻器，使用主動負載降低功率，並在轉導級電晶體汲級加上電感消除寄生電容。而實際量測後，操作頻率的輸入與輸出阻抗匹配皆有在-10dB以下，轉換增益為18.7dB，IIPᴣ為-22dBm，雜訊指數為8.63dB，而量測之功率消耗為62.3mW。
第三個主題是利用TSMC 0.18µm CMOS的製程，設計應用於802.11a頻段的接收器，採用的LNA為電流再利用的架構，而混頻器的切換級採用PMOS來降低操作電壓。模擬結果輸入與輸出阻抗皆為-10dB以下，轉換增益為31.56dB，雜訊指數為9.22dB，IIPᴣ為-32dBm， P1ɗB為-41dBm，而消耗功率為41mW。
第四個主題為利用TSMC 0.18µm CMOS的製程設計24GHz超外差系統的前端電路，利用三級疊接組態的LNA串接單端平衡混頻器來完成，使用單端平衡式混頻器可減少訊號單轉雙的困難。量測結果轉換增益為20.4dB，線性度IIPᴣ為-22dBm，P1ɗB為-12dBm，雜訊指數為8.37dB，而整體的功率消耗為64.8mW，其中核心電路只有54mW。

The thesis includes four topics. The first design topic a low noise amplifier（LNA）in W-band that used in automotive collision avoidance radar and was fabricated in TSMC 90nm CMOS process. We used coplanar waveguide transmission line for input and output matching in layout, this kind of transmission line adopted ground shielding technique to enhance Q value and decrease signal loss from substrate. This chapter will discuss about how to design the dimension of transistor and proper bias, and also to derive a lower noise figure of the transistor size and passive components from noise model. The measurement shows input and output matching are under -10dB in the operation frequency 78GHz, gain is 12.57dB, 3-dB bandwidth is 74GHz-90GHz, IIPᴣ is -8.1dBm, and noise figure is 6.07dB. Compared with previous references in the same operation frequency, our design had better noise figure. Power consumption in measurement was 28.56mW.
The second topic describes a 24GHz direct-conversion receiver which is fabricated in TSMC 0.18µm CMOS. This LNA uses three stages cascode topology to enhance gain, and employs an active balun to transfer single signal to differential. This mixer is double balanced type, and designs active loads to decrease power dissipation, it also parallels an inductor to eliminate parasitic capacitances between the drain of transistor on the transconductance stage. The measured input and output matching are under -10dB in the operation frequency, conversion gain is 18.7dB, IIPᴣ is -22dBm, and noise figure is 8.63dB. The measurement shows power consumption is 62.3mW.
The third topic implement a direct-conversion receiver applied to 802.11a fabricated in TSMC 0.18µm CMOS. LNA is current reused topology, and mixer adopts PMOS transistor at switch stage to reduce headroom. The simulation results are input and output matching are under -10dB, conversion gain is 31.56dB, IIPᴣ is -32dBm, P1ɗB is -41dBm and noise figure is 9.22dB. Power consumption is 41mW.
The forth topic introduces a 24GHz super-heterodyne receiver frontend uses in TSMC 0.18µm CMOS technology. This design uses three stages cascode topology LNA connects single balanced mixer, that can neglect the problem to transfer single signal to differential. After measurement, conversion gain is 20.4dB, IIPᴣ is -22dBm, P1ɗB is -12dBm and noise is 8.37dB. Power consumption ias 64.8mW, and core area is 54mW.

致謝.........................I
摘要（中文）...............III
Abstract....................IV
目錄........................VI
圖目錄.......................X
表目錄.....................XVI
第一章 序論
1-1研究背景..............................1
1-2文獻回顧..............................4
第二章 低雜訊放大器
2-1研究動機..............................6
2-2低雜訊放大器之重要特性................7
2-2-1 放大器雜訊參數.................7
2-2-2 穩定性.........................8
2-2-3 線性度.........................8
2-3電路設計考量與理論...................12
2-3-1 電晶體設計考量................12
2-3-2 放大器雜訊參數................13
2-3-3 77GHz CMOS低雜訊放大器雜訊最佳化之設計.......16
2-3-4 共平面波導（Coplanar waveguide，CPW）設計....20
2-4 電路架構............................22
2-5 模擬與量測..........................23
2-5-1 模擬結果與量測圖.............23
2-5-2 文獻比較表...................30
2-6 電路佈局圖..........................31
2-7 結果與討論..........................32
第三章 應用於24GHz接收電路設計
3-1架構簡介.............................33
3-1-1 直接降頻接收器（Direct-Conversion Receivers, DCR）之考量........33
3-1-2 論文設計架構..................36
3-2低雜訊放大器（LNA）之設計............37
3-2-1 電路架構......................37
3-2-2 模擬結果......................38
3-3主動巴倫器（Balun）設計..............39
3-3-1 電路簡介......................39
3-3-2 電路架構......................40
3-3-3 模擬結果......................42
3-4 混頻器（Mixer）設計.................43
3-4-1 混頻器簡介....................43
3-4-2 電路架構......................48
3-4-3 模擬結果......................52
3-5 完整電路架構........................54
3-6 模擬與量測..........................55
3-6-1 量測方法與配置...............55
3-6-2 模擬結果與量測圖.............58
3-6-3 文獻比較表...................65
3-7 電路佈局圖..........................66
3-8 結果與討論..........................67
第四章 應用於802.11a前端電路設計
4-1架構簡介.............................68
4-2低雜訊放大器之設計...................70
4-2-1 電路架構......................70
4-2-2 設計考量......................71
4-2-3 模擬結果......................73
4-3主動巴倫器（Balun）設計..............74
4-4 雙端平衡混頻器設計..................76
4-4-1 電路架構......................76
4-4-2 設計考量......................77
4-4-3 模擬結果......................77
4-5 完整電路架構........................79
4-6 模擬結果............................80
4-6-1 模擬結果圖...................80
4-6-2 文獻比較表...................83
4-7 電路佈局圖..........................85
4-8 結果與討論..........................85
第五章 24GHz超外差式接收器之前端電路
5-1超外差式接收器架構簡介...............86
5-1-1 超外差式接收器之特性..........86
5-1-2 超外差式接收器之鏡像頻率與抑制方法......86
5-1-3 中頻訊號的設定................87
5-1-4 論文設計架構..................89
5-2低雜訊放大器（LNA）之設計............90
5-2-1 疊接組態分析..................90
5-2-2 電路架構......................93
5-2-3 模擬結果......................95
5-3 混頻器（Mixer）設計.................96
5-3-1 電路架構......................96
5-3-2 模擬結果......................97
5-4 完整電路架構........................99
5-5 模擬與量測.........................100
5-5-1 量測方法與配置..............100
5-5-2 模擬結果與量測圖............102
5-5-3 文獻比較表..................109
5-6 電路佈局圖.........................110
5-7 結果與討論.........................111
6-1結論................................112
6-2未來工作目標........................113
參考文獻...............................114

[1] Behzad Razavi, “RF Microelectronics 2nd Edition”, Prentice-Hall, 2011
[2] David M.Pozar,”Microwave engineering ”, John Wiley&Sons,Inc.
[3] A. Boveda, F. Orgitoso, and J. I. Alonso, "A 0.7-3GHz QPSK/QAM direct modulator, " IEEE Journal Solid-State Circuits, vol. 28, no. 12, pp. 1340-1349, Dec. 1993.
[4] Enz, C. ," MOS transistor modeling for RF integrated circuit design," IEEE Custom Integrated Circuits Conference, CICC, pp189 - 196, 2000.
[5] Tajinder Manku , "Microwave CMOS—Device Physics and Design," IEEE Journal Solid-State Circuits, vol.34, no 3, pp277-285, Mar. 1999.
[6] Derek K. Shaeffer, Thomas H. Lee, " A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier, " IEEE Journal Solid-State Circuits, Vol. 32, no. 5, May 1997.
[7] 李亮輝, “802.11a WLAN 接收機射頻系統規劃與5GHz CMOS差動 LNA/Mixer之設計,” 國立成功大學電機工程學系碩士學位論文,June 2002.
[8] 許展榕, “低損耗傳輸線與寬頻低雜訊放大器之研究,” 國立中興大學電機工 程學系碩士學位論文, July 2008.
[9] Jri Lee, Yi-An Li, Meng-Hsiung Hung, and Shih-Jou Huang, “A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology, ” IEEE Journal of Solid-State Circuits, vol. 45, no. 12, Dec. 2010
[10] M. Fahimnia, M.R. Nezhad-Ahamadi, B. Biglarbeigian, S. Safavi-Naieni, “A 77 GHz Low Noise Amplifier Using Low-Cost 0.13μm CMOS Technology , ” Microsystems and Nanoelectronics Research Conference, pp. 73-75, 2nd 2009.
[11] Roc Berenguer, Gui Liu1, Abe Akhiyat, Keya Kamtikar, Yang Xu, “A 43.5mW 77GHz Receiver Front-End in 65nm CMOS suitable for FM-CW Automotive Radar,” IEEE Custom Integrated Circuits Conference (CICC),pp.1-4, Nov. 2010.
[12] Khanpour, M.; Tang, K.W.; Garcia, P.; Voinigescu, S.P.," A Wideband W-Band Receiver Front-End in 65-nm CMOS," IEEE Journal of Solid-State Circuits, pp1717-1730, Aug, 2008.
[13] Hsuan-Yi Su, Robert Hu, and Chung-Yu Wu, "A 78~102 GHz Front-End Receiver in 90 nm CMOS Technology," IEEE Microwave and Wireless Components Letters, vol. 21, no. 9, Sep. 2011.
[14] 葉嘉豪, “設計應用於CMOS技術之注入鎖定頻率除頻器,” 國立中興大學電機工程學系碩士學位論文, July 2011.
[15] S. Shekhar, J. S.Walling, and D. J. Allstot, “Bandwidth extension techniques for CMOS amplifiers,” IEEE Journal Solid-State Circuits, vol. 41, no.11, pp. 2424–2438, Nov. 2006.
[16] C. K. Sun, R. J. Orazi, S. A. Pappert, and W. K. Bums, " A Photonic-Link Millimeter- Wave Mixer Using Cascaded Optical Modulators and Harmonic Carrier Generation," IEEE Photonics Technology Letters, Vol. 8,no. 9, Sep. 1996.
[17] 黃家洋, “應用於無線區域網路802.11a、24GHz與60GHz之射頻接收前端電路設計,” 國立中興大學電機工程學系碩士學位論文, July 2011.
[18] Barrie Gilbert, "The MICROMIXER: A Highly Linear Variant of the Gilbert Mixer Using a Bisymmetric Class-AB Input Stage," IEEE Journal Solid-State Circuits, Vol. 32, no. 9, Sep. 1997.
[19] Behzad Razavi, " A 60-GHz CMOS Receiver Front-End ," IEEE Journal Solid-State Circuits, Vol. 41, no. 1, Jan. 2006.
[20] Jinsung Park, Chang-Ho Lee, Byung-Sung Kim, Joy Laskar, " Design and Analysis of Low Flicker-Noise CMOS Mixers for Direct-Conversion Receivers," IEEE Transactions on Microwave Theory and Techniques, Vol. 54, no. 12, pp 4372-4380, Dec. 2006.
[21] Jri Lee, Ming-Shuan Chen, and Huai-De Wang,” Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data”, IEEE Journal of Solid-State Circuits, pp.2120-2133, Sep. 2008.
[22] Kenichi Kawasaki, Yoshiyuki Akiyama, Kenji Komori, Masahiro Uno, Hidenori Takeuchi, Tomoari Itagaki, Yasufumi Hino, Yoshinobu Kawasaki, Katsuhisa Ito, Ali Hajimiri, "Millimeter-Wave Intra-Connect Solution," IEEE Journal of Solid-State Circuits, pp2655-2666, Vol. 45, No. 12, Dec. 2010.
[23] Yu-Hsin Chen, Hsieh-Hung Hsieh, Liang-Hung Lu,” A 24-GHz Receiver Frontend With an LO Signal Generator in 0.18- CMOS,” IEEE Transactions on microwave theory and techniques, pp1043-1051, Vol. 56, no. 5, May 2008.
[24] Xiang Guan, Ali Hajimiri, " A 24-GHz CMOS Front-End," IEEE Journal of Solid-State Circuits, pp368-373, Vol. 39, No. 2, Feb. 2004.
[25] Chen-Yuan Chu, Chien-Cheng Wei, Hui-Chen Hsu, Shu-Hau Feng, Wu-Shiung Feng, “A 24GHz Low-Power CMOS Receiver Design, ” IEEE International Symposium on Circuits and Systems, ISCAS, pp980-983, May 2008.
[26] Mohamed El-Nozahi, Ahmed Amer, Edgar Sánchez-Sinencio, Kamran Entesari, "A Millimeter-Wave (24/31-GHz) Dual-Band Switchable Harmonic Receiver in 0.18- SiGe Process," IEEE Transactions on Microwave Theory and Techniques, Vol. 58, no. 11, Nov. 2010.
[27] Yu-Lin Wei, Shawn S. H. Hsu, Jun-De Jin, “A Low-Power Low-Noise Amplifier for K-Band Applications, ” IEEE Microwave and Wireless Components Letters, pp116-118, Vol. 19, no. 2, Feb. 2009.
[28] Hsieh-Hung Hsieh and Liang-Hung Lu, “Design of ultra-low-voltage RF frontends with complementary current-reused architectures,” IEEE Trans. Microwave Theory Techniques, vol. 55, no. 7, pp. 1445–1458, Jul. 2007.
[29] Hsieh-Hung Hsieh, Huan-Sheng Chen, Ping-Hsi Hung, and Liang-Hung Lu, "Experimental 5-GHz RF Frontends for Ultra-Low-Voltage and Ultra Low Power Operations," IEEE Transactions on Very Large Scale Integration（VLSI）Systems, pp705-709, Vol. 19, no. 4, Apr. 2011.
[30] Sining Zhou,and Mau-Chung Frank Chang,” A CMOS Passive Mixer With Low Flicker Noise for Low-Power Direct-Conversion Receiver”, IEEE Journal of Solid-State Circuits, pp.1084-1093, May 2005.
[31] Azevedo, F. , Fortes, F. , Rosario, M.J. , "A 1.8V/5.2GHz WLAN CMOS RFIC Receiver," IEEE International Conference on Computer as a Tool (EUROCON), pp.1-4, Apr. 2011.
[32] Mihai A. Margarit, David Shih, Patrick J. Sullivan, and Fernando Ortega "A 5-GHz BiCMOS RFIC Front-End for IEEE 802.11a/HiperLANWireless LAN," IEEE Journal of Solid-State Circuits, Vol.38, no.7, pp1284-1287, Jul. 2003.
[33] 王繼豪, “應用於頻率合成器之高性能子電路之研製,” 國立中興大學電機工程學系碩士學位論文, July 2011.
[34] T. K. Nguyen, C. H. Kim, G. J. Ihm, M. S.Yang, and S. G. Lee, “CMOS low-noise amplifier design optimization tehcniques,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 5, pp. 1433–1442, May 2004.
[35] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge, U.K.: Cambridge Univ. Press, 1998.
[36] Xiaohua Fan, Heng Zhang, Edgar Sánchez-Sinencio, "A Noise Reduction andLinearity Improvement Technique for a Differential Cascode LNA,"IEEEJournal Solid-State Circuits, Vol. 43, no. 3,pp. 588-599, Mar. 2008.
[37] Heng Zhang, Xiaohua Fan, and Edgar Sánchez Sinencio, " A Low-Power, Linearized, Ultra-Wideband LNA Design Technique," IEEE Journal Solid-State Circuits, Vol. 44, no. 2,pp. 320-330, Feb. 2009.
[38] W. Zhuo, S. H. K. Embabi, J. Pineda de Gyvez, and E. Sánchez-Sinencio, “Using capacitive cross-coupling technique in RF low-noise amplifiers and down conversion mixer design,” in Proc. Eur.Solid-State Circuits Conf. (ESSCIRC), pp. 116–119, Sep. 2000.
[39] T. H. Lee, H. Samavati, and H. R. Rategh, “5-GHz CMOS wireless LANs,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 268–280, Jan. 2002.
[40] H. Samavati, H. R. Rategh, and T. H. Lee, “A 5-GHz CMOS wireless LAN receiver front-end,” IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 765–772, May 2000.
[41] W. Zhuo, X. Li, S. Shekhar, S. H. K. Embabi, J. Pineda de Gyvez, D. J. Allstot, and E. Sánchez-Sinencio, “A capacitor cross-coupled common-gate low noise amplifier,” IEEE Trans. Circuits Syst. II: Expr. Briefs, vol. 52, no. 12, pp. 875–879, Dec. 2005.
[42] 張綺真, “應用於無線區域網路802.11a/b/g與60GHz之低雜訊放大器設計,” 國立中興大學電機工程學系碩士學位論文, July 2011.
[43] Vipul Jain, Sriramkumar Sundararaman, Payam Heydari, " A 22–29-GHz UWB Pulse-Radar Receiver Front-End in 0.18- m CMOS," IEEE Transactions on Microwave Theory and Techniques, Vol. 57, no. 8, pp1903-1914, Aug. 2009.
[44] Andrea Mazzanti, Marco Sosio, Matteo Repossi, Francesco Svelto, " 24 GHz Subharmonic Direct Conversion Receiver in 65 nm CMOS," IEEE Transactions on Circuits and Systems, Vol. 58, no. 1, pp88-97, Jan. 2011.