臺灣博碩士論文加值系統

在本論文中，我們分別針對了三種不同運用、結構及操作電壓的整合型高壓金氧半電晶體進行熱載子可靠性研究與製程條件關聯性之分析。最後成功研發出與世界一流大廠性能相當的整合型高壓高功率製程。
研究顯示，若比較0.5 um 40V操作N通道之汲極延伸型(N-type DEMOS)高壓金氧半電晶體與傳統之低電壓MOS元件其熱載子之可靠性，至少有三種明顯不同的現象 – Kirk effect加速了元件的退化、閘極偏壓愈大退化程度也愈大、以及元件退化會回復(recovery)。這些現象導致此種汲極延伸型(DEMOS)高壓金氧半電晶體的熱載子可靠度與低電壓MOS元件有明顯的不同。藉由實驗結果與二維製程及電性模擬分析，我們證實在高汲極偏壓測試條件下，閘極偏壓愈大因Kirk effect使得處於元件飄移區之最大撞擊游離區越往汲極接近，同時在通道區產生之電場也越強。由於熱載子產生的缺陷越靠近汲極，其閘極的控制能力越弱，使得導通電阻退化越大。而通道區之強電場所產生的缺陷則使得電導的退化隨著閘極偏壓變大而變大。此外，元件退化回復的現象使得元件在低頻交流操作條件下，其熱載子壽命可趨近於無窮長。
對於0.5 um 12V N通道汲極延伸型(N-type DEMOS)高壓金氧半電晶體，我們則探討不同汲極飄移區離子佈植(NDD)濃度對元件可靠度之影響，發現了一個異常的熱載子退化現象。於相同的測試條件下，NDD濃度越高則基極電流越大，元件最大電導退化有輕微增加但是導通電阻退化卻大幅變小。由實驗結果與二維模擬分析，我們證實有兩種不同的退化機制同時發生。其一是發生於接近通道的累積區之熱電子注入，其二是發生在接近間隙壁的累積區之熱電洞注入。熱電洞的注入在閘極氧化層裡產生帶正電的陷阱，導致累積區感應出帶負電的鏡射電子而使得導通電阻電小，此一機制被證實為導通電阻異常退化的主因。
另外，我們針對高功率整合型電源管理積體電路所開發的0.35 um 12V超低導通電阻N通道高電壓橫向擴散金氧半電晶體(LDMOS)，分析元件的熱載子可靠性，結果顯示因為Kirk effect的緣故，調整閘極累積區(NDD)的ｎ型參雜濃度，會使得最大的基極電流發生在不同的閘極偏壓。當NDD濃度越高，第一個基極電流峰值越大，但第二個峰值越小。當閘極偏壓在第一個基極電流峰值時，由於熱電洞注入在閘極累積區產生acceptor type介面態interface traps (Nit)，acceptor type Nit填入電子後帶負電因排斥而使電子濃度減低使得導通電阻變大。當閘極偏壓在第二個基極電流峰值時，通道區的強電場導致熱電子注入而產生donor type Nit使得元件最大電導嚴重退化，連帶影響導通電阻退化變大。
由於電源管理電路之設計特殊，0.35 um 12V高電壓橫向擴散金氧半電晶體會因為外掛電感器所產生的電壓突波衝擊導致纍增崩潰而引起電晶體之退化。我們以定電流脈波測試來模擬電壓突波衝擊對元件可靠性的影響，發現橫向擴散金氧半電晶體的崩潰電壓，導通電阻與臨界電壓都隨著測試次數的增加而變大，並且在一段時間後都呈現飽和的狀態。藉由二維模擬與電荷幫浦實驗的分析，我們證實是熱電洞注入發生在接近間隙壁的累積區，產生帶負電的介面態使得導通電阻變大，同時局部電場強度因為帶負電的介面態產生而減底使得崩潰電壓也變大。此一現象可經由外加限壓元件或電路來避免。另外因其退化會飽合之特性，元件在出廠前可加做電性熟成來改善退化的程度。
最後，我們成功開發了一0.35um 12V BCD製程其中提供了雙載子電晶體，標準互補式金氧半場效電晶體及崩潰電壓21V，導通電阻0.7mW-mm2的高性能12V高電壓橫向擴散金氧半電晶體。這個製程不僅展示了我們的技術能力，同時讓設計公司有機會設計出更小、更節能、更具競爭力的電源管理晶片。

In this dissertation, the integrated high-voltage MOSFET with three different kinds of application, structure and operation voltage are studied and analyzed on hot-carrier reliability and process conditions correlations.
Comparing the hot-carrier reliability of 0.5um 40V N-type drain extended MOSFET (DEMOS) transistors to the conventional low-voltage CMOS transistors; there are there kinds of obviously phenomena – Kick effect accelerated the device degradation, the degradation is proportional to the gate bias and degradation recovery. The hot-carrier reliability behavior of this DEMOS transistor is thus very different from the conventional CMOS transistors. According to the experimental results and two-dimensional process and electric simulation analysis, we identify that under a fixed drain voltage, devices stressed at a higher Vgs results in a greater maximum transconductance (Gmmax) and on-resistance (Ron,sp) degradation. Under higher Vgs, the increase in channel hot-carrier injection is responsible for the greater Gmmax degradation. On the other hand, Kirk effect induced increase in drain avalanche hot carriers near the drain as well as higher electric field in the channel is responsible for the greater Ron degradation. Second, AC lifetime is much longer than DC lifetime because of the recovery in degradation.
An anomalous hot-carrier degradation phenomenon was observed in 0.5mm 12V N-type drain extended MOS transistors (N-DEMOS) with various n-type drain drift (NDD) implant dosage. Under the same stress condition, the device with higher NDD dosage produces higher substrate current, slightly higher transconductance degradation (Gmmax), but lower on-resistance (Ron,sp) degradation. Two degradation mechanisms are identified from the analysis of electrical data and two-dimensional device simulations. The first mechanism is hot electron injection in accumulation region near the junction of channel and accumulation region. The second mechanism is hot hole injection in the accumulation region near the spacer. This injection of hot holes creates positive charge trapping in the gate oxide, resulting in negative mirror charges in accumulation region that reduces Ron,sp. The second mechanism is identified to account for the anomalous lower Ron degradation.
For high power management integrated circuit (PMIC) product, we develop a 0.35 um 12V N-type lateral double diffuse MOSFET (LDMOS) transistor, and study hot-carrier reliability accordingly. The maximum bulk current (Ib) occurs at different gate bias on various NDD dosages under the Poly gate accumulation region. Under higher NDD dosage, the first bulk current peak is higher, but the second peak is lower. When the gate bias under the first bulk current peak, both the acceptor-type and donor-type interface traps (Nit) are generated simultaneously by the hot hole injection at gate accumulation region and hot electron injection at channel region, respectively. Acceptor-type Nit induced positive charges and results in higher Ron, however, the stress in higher NDD device generated positive charge oxide traps that induced negative charges and results in lower Ron. When device is stressed under the gate bias at second bulk current peak, the additional channel high electric field damage results in serious Gmmax degradation and thus larger Ron degradation.
Because of the special design of power management IC, the current surge and voltage spike occur on the drain of LDMOS transistors forced the unclamped device into the avalanche break down, when inductive load switching, and induced device degradation. With fixed current pulse stress, the break down voltage (BVdss), Ron,sp and threshold voltage (Vth) become higher and trend to saturate after several stress times. Break down induced hot holes injections generate a lot of acceptor-type Nit under Poly edge will dynamically change the micro electric field and increase the break down voltage. Acceptor-type Nit attracts electrons and increases the drain series resistance and results in Ron degradation.
At last, we deliver an excellent high-voltage 035um 12V Bipolar, CMOS, DMOS (BCD) technology with 21V BVdss and 7 mW-mm2 Ron high performance N-type LDMOS, which demonstrates our technology capability and enable the fabless companies to design the smaller, higher efficiency and more competitive PMIC products.

Abstract (Chinese) II
Abstract (English) V
Acknowledgement IX
Contents XI
Table Captions XIII
Figure Captions XIV

Chapter 1 Introduction 1
1.1 Applications of Integrated High Voltage Technologies 1
1.2 Organization of this Dissertation 3
Reference 6
Chapter 2 Process Integration and Reliability Challenge of High Voltage Devices 12
2.1 High Voltage Devices Overview 12
2.2 Process Integration of High Voltage Technology 15
2.3 Safe Operating Area 16
2.4 Introduction of Charge Pumping Technique 18
Reference 21
Chapter 3 Hot-Carrier Reliability in Submicrometer 40V DEMOS Transistors with Thick Gate Oxide 33
3.1 Introduction 33
3.2 Experimental Details 34
3.3 Effect of Gate Bias 35
3.4 Degradation Recovery 39
3.5 Conclusion 40
Reference 42
Chapter 4 Anomalous Reduction of Hot-Carrier-Induced On-Resistance Degradation in 12V N-type DEMOS Transistors 54
4.1 Introduction 54
4.2 Device Description 56
4.3 Experimental Results 57
4.4 Discussion 60
4.5 Conclusion 63
Reference 64
Chapter 5 Hot-Carrier Reliability in Integrated LDMOS Transistors 81
5.1 Motivation 81
5.2 Device Description 84
5.3 Low Stress Gate Voltage with Various NDD Dosages 87
5.4 Fix NDD in Medium Dosage and Various Stress Gate Voltage
92
5.5 Conclusion 95
Reference 97
Chapter 6 Break Down Induced Degradation in 12V NLDMOS Transistors 115
6.1 Motivation 115
6.2 Device Description 117
6.3 Experimental Results 118
6.4 Discussion 120
6.5 Conclusion 122
Reference 123
Chapter 7 Conclusion and Prospect 134
7.1 Conclusions 134
7.2 Prospect 135
Reference 137
Vita 140
Publication List 141

Chapter 1
[1] C. Contiero, B. Murari and B. Vigna, “Process in Power ICs and MEMS, Analog Technologies to interface the Real World,” in Proceedings of ISPSD, pp. 3-12, 2004.
[2]E. Stanford, “Microprocessor Voltage Regulators Power Supply Trends and Device Requirements,” in Proceedings of ISPSD, pp. 47-50, 2004.
[3] M. Darwish, “Low Voltage Power Devices for Portable Systems Low Voltage Power Devices for Portable Systems,” in short courses of ISPSD, p. 3, 2005.

Chapter 2
[1] P. Hower, “Safe Operating Area – A New Frontier in LDMOS Design,” Proc. ISPSD’02, pp. 1-8, 2002.
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[4] P. Hower and S. Pendharkar, “Short and Long-Term Safe Operating Area Considerations in LDMOS Transistors” in Proc. IRPS’05, pp. 545-550, 2005
[5] P. Moens, G. Bosch “Characterization of Total Safe Operating Area of Lateral DMOS Transistors” IEEE Trans. Device and Materials Reliability, vol. 6, pp. 349-357, 2006.
[6] P. Hower, J. Lin and S. Merchant, “Snapback and Safe Operation Area of LDMOS Transistors” in IEDM Techn. Dig, pp. 193-196, 1999.
[7] Y.S. Chung, “Junction Temperature Induced Thermal Snapback Breakdown of MOSFET Device,” IEEE Electron Device Letters, 23, pp. 615-617, 2002.
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[17] R. Versari and A. Pieracci, “Experimental Study of hot-Carrier Effects in LDMOS Transistors,” IEEE Transactions on Electron Devices, 46, pp. 1228-1233, 1999.
[18] V. O’Donovan, S. Whiston, A. Deignan, C.N. Chleirigh, “Hot Carrier Reliability of Lateral DMOS Transistors,” Proc. of the Int. Reliability Physics Symp., pp. 174-179, 2000.
[19] S. Manzini, A. Gallerano, “Avalanche Injection of Hot Holes in the Gate Oxide of LDMOS Transistors,” Solid-State Electronics, 44, pp. 1325-1330, 2003.
[20] D. Brisbin, A. Strachan, P. Chaparala, “Hot Carrier Reliability of NLDMOS Transistor Arrays for Power BiCMOS Applications, Proc. of the Int. Reliability Physics Symp., pp. 105-110, 2002.
[21] L. Labate, S. Manzini, R. Rogerro, “Hot-Hole-Induced Dielectric Breakdown in LDMOS transistors,” IEEE Transactions on Electron Devices, 50, pp. 372-377, 2004.
[22] P. Moens, M. Tack, R. Degraeve and G. Groeseneken, “A Novel Hot-Hole Injection Degradation Mechanism for Lateral nDMOS Transistors,” IEDM Techn. Dig., pp. 877- 880, 2001.
[23] P. Heremans, J. Witters, G. Groeseneken and H. Maes, “Analysis of the Charge Pumping Technique and Its Applications for the Evaluation of MOSFET Degradation,” IEEE Trans. Electron Devices, vol. 36, no. 7, pp. 1318–1335, 1989.
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Chapter 3
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[2]R. Versari, and A. Pieracci, “RF LDMOS with extreme low parasitic feedback capacitance and highhot-carrier immunity,“IEEE Trans. Electron Devices, 46, pp. 1228-1233, 1999.
[3]D. Brisbin, Andy Strachan, and P. Chaparala, “Hot carrier reliability of N-LDMOS transistor arrays for power BiCMOS applications,“ in Proc. IEEE International Reliability Physics Symposium, pp. 105-110, 2002.
[4]S. K. Lee, C. J. Kim, J. H. Kim, Y. C. Choi, H. S. Kang, and C. S. Song, “Optimization of safe-operating-area using two peaks of body-current in submicron LDMOS transistors,” in Proc. IEEE ISPSD, pp. 287-290, 2001.
[5] E. Li, E. Rosenbaum, and P. Fang, “Projecting lifetime of deep submicron MOSFETs “, IEEE Trans. Electron Devices, 48, pp. 671-678, 2001.
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[14]S. Rangan, N. Mielke, and E. C. C. Yeh, “Universal recovery behavior of negative bias temperature instability,” in IEDM Tech. Dig., pp. 341-344, 2003.
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Chapter 4
[1] S. Manzini and C. Contiero, “Hot-electron-induced degradation in high-voltage submicron DMOS transistors,” in Proceedings of ISPSD, pp. 65-68, 1996.
[2]R. Versari, A. Pieracci, S. Manzini, C. Contiero, and B. Ricco, “Hot-carrier reliability in submicrometer LDMOS transistors,” in IEDM Tech. Dig. 7, pp. 371-374, 199.
[3]A. W. Ludikhuize, M. Slotboom, A. Nezar, N. Nowlin, and R. Brock, “Analyasis of hot-carrier-induced degradation and snapback in submicron 50V lateral MOS transistors,” in Proceedings of ISPSD, pp. 53-56, 1997.
[4]V. O’Donovan, S. Whiston, A. Deignan, and C. N. Chleirigh, “Hot carrier reliability of lateral DMOS transistors,” in Proceedings of IRPS, pp. 174-179, 2000.
[5] P. Moens, M. Tack, R. Degraeve, and G. Groeseneken, “A novel hot-hole injection degradation model for lateral nDMOS transistors,” in IEDM Tech. Dig., 2001, pp. 877-880, 2001.
[6]S. K. Lee, C. J. Kim, J. H. Kim, Y. C. Choi, H. S. Kang, and C. S. Song, “Optimization of safe-operating-area using two peaks of body-current in submicron LDMOS transistors,” in Proceedings of ISPSD, pp. 287-290, 2001.
[7]D. Brisbin, A. Strachan, and P. Chaparala, “Hot carrier reliability of N-LDMOS transistor arrays for power BiCMOS applications,” in Proceedings of IRPS, pp. 105-110, 2002.
[8] P. Moens, G. V. den bosch, and G. Groeseneken, “Competing hot carrier degradation mechanisms in lateral n-type DMOS transistors,” in Proceedings of IRPS, pp. 214-221, 2003.
[9] P. Moens, G. V. den bosch, C. De Keukeleire, R. Degraeve, M. Tack, and G. Groeseneken, “Hot hole degradation effects in laternal nDMOS transistors, “ IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1704-1710, 2004.
[10] P. L. Hower and S. Pendharkar, “Short and long-term safe operating area considerations in LDMOS transistors,” in Proceedings of IRPS, pp. 545-550, 2005.
[11] J. F. Chen, K.-M. Wu, K.-W. Lin, Y.-K. Su, and S. L. Hsu, “Hot-carrier reliability in submicrometer 40V LDMOS transistors with thick gate oxide,” in Proceedings of IRPS, pp. 560-564, 2005.
[12] S. K. Manhas, M. M. De Souza, A. S. Oates, S. C. Chetlur and E. M. Sankara Narayanan, “Early Stage Hot Carrier Degradation of state-of-the-art LDD N-MOSFETs,” in Proceedings of IRPS, pp. 108-111, 2000.
[13] P. Heremans, J. Witters, G. Groeseneken and H. E. Maes, “Analysis of the Charge Pumping Technique and Its Application for the Evaluation of MOSFET Degradation,” IEEE Trans. Electron Devices, Vol. 36, NO. 7, pp. 11318-1334, 1989.
[14] S. Tam, P. Ko and C. Hu, “Lucky-Electron Model of Channel Hot-Electron Injection in MOSFETs,” IEEE Trans. Electron Devices, Vol. ED-31, pp. 1116-1125, 1984.
[15] Y. Pan, K.K. Ng and C. C. Wei, “Hot-Carrier Induced Electron Mobility and Series Resistance Degradation in LDD NMOSFET’s,” IEEE Electron Devices Letters, vol. 15, no. 12, pp. 499-501, 1994.
[16] G. Krieger, R. Sikora, P. P. Cuevas and M. N. Misheloff, “Moderately Doped NMOS (M-LDD) – Hot Electron and Current Driver Optimization,” IEEE Trans. Electron Devices, vol. 38, no. 1, pp. 121-127, 1991.
[17] S.-H. Chen, J. Gong, M.-C. Wu, T.-Y. Huang, J.-F. Huang, R.-H. Liou, S.-L. Hsu, L-L. Lee, and H. C. Lee, “Time-dependent drain- and source-series resistance of high-voltage lateral diffused metal-oxide-semiconductor field-effect transistors during hot-carrier stress,” Jpn. J. Appl. Phys., vol. 42, part 1, no. 2A, pp. 409-413, 2003.

Chapter 5
[1] C. Y. Tsai et al., “16–60 V rated LDMOS show advanced performance in an 0.72 mm evolution BiCMOS power technology,” in IEDM Tech. Dig., pp. 367-370, 1997.
[2] V. Parthasarathy et al., “A 33 V, 0.25 mW - cm n-channel LDMOS in a 0.65 mm smart-power technology for 20-30 V operation,” in Proc. Int. Symp. Power Semiconductor Dev., pp. 61-64, 1998.
[3] J. A. Van der Pol et al., “A-BCD: An economic 100 V RESURF silicon-on-insulator BCD technology for consumer and automotive applications,” in Proc. Int. Symp. Power Semiconductor Dev., pp. 327-330, 2000.
[4] T. Terashima et al., “Multi-voltage device integration technique for 0.5 mm BiCMOS and DMOS process,” in Proc. Int. Symp. Power Semiconductor Dev., pp. 331-334, 2000.
[5] Y. Kawagushi et al., “0.6 mm BiCMOS-based 15 and 25 V LDMOS for analog applications,” in Proc. Int. Symp. Power Semiconductor Dev., pp. 169-172, 2001.
[6] P. Moens et al., “I3T80: A 0.35 mm based system-on-chip technology for 42 V battery automotive applications,” in Proc. Int. Symp. Power Semiconductor Dev., pp. 225-228, 2002.
[7] R. Versari, A. Pieracci, S. Manzini, C. Contiero and B. Ricco “ Hot Carrier Reliability in Submicrometer LDMOS transistors,” in IEDM Techn. Dig., pp. 371-373, 1997.
[8] V.O’Donovan, S. Whiston, A. Deignan, C.N. Chleirigh, “Hot carrier reliability of lateral DMOS transistors,” Proc. of the Int. Reliability Physics Symp., pp. 174-179, 2000.
[9] S. Manzini, A. Gallerano, “Avalanche injection of hot holes in the gate oxide of LDMOS transistors,” Solid-State Electronics, 44, pp. 1325-1330, 2003.
[10] D. Brisbin, A. Strachan, P. Chaparala, “Hot carrier reliability of NLDMOS transistor arrays for power BiCMOS applications,” Proc. of the Int. Reliability Physics Symp, pp. 105-110, 2002.
[11] L. Labate, S. Manzini, R. Rogerro, “Hot-Hole-Induced Dielectric Breakdown in LDMOS transistors,” IEEE Transactions on Electron Devices, 50, pp. 372-377, 2004.
[12] P. Moens, M. Tack, R. Degraeve and G. Groeseneken, “A Novel Hot-Hole Injection Degradation Mechanism for Lateral nDMOS Transistors,” IEDM Techn. Dig., pp877- 880, 2001.
[13] A.W. Ludikhuize, “Kirk effect limitations in high voltage IC's,” in Proc. Int. Symp. Power Semiconductor, pp. 249–252. ISPSD, 1994.
[14] P. Heremans et al., “Analysis of the Charge Pumping Technique and Its Applications for the Evaluation of MOSFET Degradation,” IEEE Trans. Electron Device, 36, pp. 1318-1335, 1989.
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Chapter 6
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[3] J. A. Van der Pol, A. W. Ludikhuize, H. G. A. Huizing, B. Van Velzen, R. J. E. Hueting, J. F. Mom, G. Van Lijnschoten, G. J. J. Hessels, E. F. Hooghoudt, R. Van Huizen, M. J. Swanenberg, J. H. H. A. Egbers, F. Van den Elshout, J. J. Koning, H. Schligtenhorst and J. Soeteman, “A-BCD: An economic 100 V RESURF silicon-on-insulator BCD technology for consumer and automotive applications,” in Proc. Int. Symp. Power Semiconductor Dev., pp. 327-330, 2000.
[4] T. Terashima, F. Yamamoto and K. Hatasako, “Multi-voltage device integration technique for 0.5 mm BiCMOS and DMOS process,” in Proc. Int. Symp. Power Semiconductor Dev., pp. 331-334, 2000.
[5] Y. Kawagushi, K. Nakamura, K. Karouji, K. Watanabe, Y. Yamaguchi and A. Nakagawa, “0.6 mm BiCMOS-based 15 and 25 V LDMOS for analog applications,” in Proc. Int. Symp. Power Semiconductor Dev., pp. 169–172, 2001.
[6] P. Moens, D. Bolognesi, L. Delobel, D. Villanueva, H. Hakim, S. C. Trinh, K. Reynders, F. De Pestel, A. Lowe, E. De Backer, G. Van Herzeele and M. Tack,” I3T80: A 0.35 mm based system-on-chip technology for 42 V battery automotive applications,” in Proc. Int. Symp. Power Semiconductor Dev., pp. 225–228, 2002.
[7] K. Dierberger, “ Understanding The Differences Between Standard MOSFETs and Avalanche Energy Rated MOSFETs”, in Prod. PCIM, pp. 1-9, 1994
[8] E. Li, E. Rosenbaum, and P. Fang, “Projecting lifetime of deep submicron MOSFETs,” IEEE Trans. Electron Devices, 48, pp. 671-678, 2001.
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Chapter 7
[1] R. Zhu, V. Khemka, A. Bose and T. Roggenbauer, “Stepped-Drift LDMOSFET: A Novel Drift Region Engineered Device for Advanced Samrt Power Technologies,” in Proceedings of ISPSD, pp. 333-336, 2006.
[2] R. Pen, B. Todd, R. Hao, R. Higgins, D. Robinson, V. Drobny, W. Tian, J. Wang, J. Mitris, M. Huber, S. Pillai and S. Pendharkar, “High Voltage (up to 20V) Devices Implementation in 0.13 um BiCMOS Process Technology for System-On-Chip (SOC) Design,” in Proceedings of ISPSD, pp. 349-352, 2006.