臺灣博碩士論文加值系統

在本論文中，藉由台積電 0.35μm的CMOS製程完成了一階低雜訊放大器、二階低雜訊放大器和一個降頻混波器的設計與實現。一階的低雜訊放大器經過量測擁有2.78 dB的順向增益(Forward Gain)及4.2 dB 的雜訊指數(Noise Figure)。而二階的低雜訊放大器被設計為23.22 dB的順向增益及2.95 dB 的雜訊指數。降頻混波器是使用吉爾伯特式的架構來設計，它提供了2.63 dB的轉換增益(Conversion Gain)，其輸入三階交叉點(IIP3)為—5.86 dBm。

In this thesis, a one-stage LNA, a two-stage LNA and a downconversion mixer have been designed and implemented with TSMC 0.35μm SPQM CMOS technology. A one-stage LNA with 2.78 dB forward gain and 4.2 dB noise figure is measured. Also designed are a two-stage LNA with a forward gain of 23.22 dB and a noise figure of 2.95 dB, and a downconversion mixer based on the Gilbert cell type with a conversion gain of 2.63 dB and an IIP3 of —5.86 dBm.

ABSTRACTI
TABLE OF CONTENTSII
LIST OF FIGURESIV
LIST OF TABLESVI
CHAPTER 1 INTRODUCTION1
1.1 MOTIVATIONS1
1.2 DESIGN GOALS OF LNA AND MIXER1
1.3 THESIS ORGANIZATION2
CHAPTER 2 RECEIVER ARCHITECTURE OVERVIEW4
2.1 INTRODUCTION4
2.2 GENERAL CONSIDERATION FOR RECEIVER5
2.3 HETERODYNE RECEIVER7
2.3.1 FREQUENCY TRANSLATION7
2.3.2 THE IMAGE PROBLEM OF THE HETERODYNE RECEIVER9
2.3.3 THE INTERMEDIATE FREQUENCY OF THE HETERODYNE RECEIVER10
2.3.4 THE DUAL-IF HETERODYNE RECEIVER11
2.4 HOMODYNE RECEIVER12
2.4.1 THE DC OFFSETS AND THE LO LEAKAGE14
2.4.2 THE EVEN-ORDER DISTORTION PROBLEM OF THE HOMODYNE RECEIVER15
2.5 RECEIVER FUNDAMENTALS16
2.5.1 GAIN AND STABILITY17
2.5.2 NOISE22
2.5.3 LINEARITY25
CHAPTER 3 LOW NOISE AMPLIFIER28
3.1 INTRODUCTION28
3.2 COMPONENT DESIGN29
3.2.1 MOSFET RF MODEL29
3.2.2 PLANAR INDUCTOR32
3.2.3 CAPACITORS36
3.3 ONE-STAGE LNA DESIGN37
3.3.1 CIRCUIT TOPOLOGY37
3.3.2 CIRCUIT DESIGN39
3.3.3 SIMULATION RESULTS42
3.4 TWO-STAGE LNA DESIGN45
3.4.1 CIRCUIT TOPOLOGY45
3.4.2 CIRCUIT DESIGN46
3.4.3 SIMULATION RESULTS47
3.5 SUMMARY49
CHAPTER 4 DOWNCONVERSION MIXER51
4.1 INTRODUCTION51
4.2 CIRCUIT TOPOLOGY52
4.3 CIRCUIT DESIGN55
4.3.1 CONVERSION GAIN55
4.3.2 NOISE FIGURE56
4.4 SIMULATION RESULTS57
4.4.1 SIMULATION RESULTS OF LO INPUT POWER, CONVERSION GAIN AND NOISE FIGURE57
4.4.2 SIMULATION RESULTS OF P-1DB AND IP360
4.5 SUMMARY62
CHAPTER 5 ONE-STAGE LNA MEASUREMENT64
5.1 MEASUREMENT SETUP64
5.2 MEASUREMENT RESULTS66
CHAPTER 6 CONCLUSIONS68
6.1 CONCLUSIONS68
CHAPTER 7 FUTURE WORK70
7.1 FUTURE WORK70
REFERENCE72

[1] P. R. Gray and R.G. Meyer, Analysis and Design of Analog Integrated Circuits, 3rd Edition, John Wiley & Sons Inc., 1993.
[2] B. Razavi, RF Microelectronics, Prentice Hall Inc., 1998.
[3] A. A. Abidi, “Direct-conversion radio transceivers for digital communications”, IEEE J. Solid-State Circuits, vol. 30, pp. 1399-1410, Dec. 1995.
[4] B. Razavi, “Design consideration for direct-conversion receivers”, IEEE Trans. Circuits Sysi., Part II, Vol.44, pp. 428-435, Jan. 1997.
[5] B. Razavi, “Architectures and circuits for RF CMOS receivers”, Proc. IEEE Custom Integrated Circuits Conf., 1998, pp. 393-400.
[6] U. L. Rohde and D. P. Newkirk, RF/Microwave Circuit Design for wireless Applications, John Wiley & Sons Inc., 2000.
[7] R. Ludwig and P. Bretchko, RF Circuit Design Theory and Applications, Prentice Hall Inc., 2000.
[8] G. Gonzales, Microwave Transistor Amplifiers: Analysis and Design, 2nd Edition, Prentice Hall Inc., 1997.
[9] D. M. Pozar, Microwave Engineering, 2nd Edition, John Wiley & Sons Inc., 1998.
[10] B. K. Ko and K. Lee, “ A Comparative Study on the Various Monolithic Low Noise Amplifier Circuit Topologies for RF and Microwave Application”, IEEE J. Solid-State Circuits, vol. 31, pp. 1220-1225, Aug. 1996.
[11] J. Chang, “An integrated 900MHz Spread-Spectrum Wireless Receiver in 1-um CMOS and a Suspended Inductor Technique: Final Report”, Integrated Circuits & System Laboratory, EE Department, UCLA, March 1998.
[12] S. Wu and B. Razavi, “A 900-MHz/1.8-GHz CMOS Receiver for Dual-Band Applications”, IEEE J. Solid-State Circuits, Vol. 33, No. 12, pp. 2178-2185, Mar. 1998.
[13] Y. S. Huang, “Design and Realization of 2.4 GHz CMOS RF Front-end Receiving Circuit”, MS Thesis, EE Department, NTU, Jun. 2000.
[14] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits,
[15] F. Sve`to, M. Conta, V. D. Torre and R. Castello, “A Low-Voltage Topology For CMOS RF mixer”, IEEE Transactions on Consumer Electronics, Vol. 45, No. 2, pp. 299-309, May 1999.
[16] P. J. Sullivan, B. A. Xavier, and W. H. Ku, “A 1.9GHz double balance dual gate downconversion mixer in 0.8μm CMOS”, in Proc. IEEE MTT-S Symposium on Technologies for Wireless Application Digest, pp. 159-162, 1997.
[17] H. Kilicaslan, H. S. Kim and M. Ismail, “A 1.9GHz RF down-conversion mixer”, in Proc. 40th Midwest Symp. Circuits Syst., Vol. 2, pp. 1172-1174, 1998.
[18] S. Y. Hsiao and C. Y. Wu, “A parallel structure for CMOS four-quadrant analog multipliers and its application to a 2-GHz RF downconversion mixer”, IEEE J. Solid-State Circuits, Vol. 33, No. 6, pp. 859-869, Jan. 1998.
[19] W. Jin, C. H. Chan and C. Hai, “1.5-V 1.8-GHz SOI low noise amplifiers for PCS receivers”, 1999 IEEE International SOI Conference, pp. 16-17, Oct. 1999.
[20] R. A. Johnson, P. R. Houssaye, C. E. Chang, P. F. Chen, M. E. Wood, G. A.Garcia, I. Lagnado and P. M. Asbeck, “Advanced thin-film silicon-on-sapphire technology: microwave circuit applications”, IEEE Transactions on electron devices, Vol. 45, No. 5, pp. 1047-1054, May 1998.
[21] M. Harada, C. Yamaguchi and T. Tsuchiya, “Investigation of a multigigahertz MOSFET amplifier with an on-chip inductor fabricated on a SIMOX wafer”, IEEE Transactions on electron devices, Vol. 45, No. 1, pp.173-178, Jan. 1998.
[22] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier”, IEEE J. Solid-State Circuits, Vol. 32, No. 5, pp. 745-759, May 1997.
[23] C.Y. Wu and S.Y. Hsiao, “The design of a 3-V 900-MHz CMOS bandpass amplifier”, IEEE J. Solid-State Circuits, Vol. 32, No. 2, pp. 159-168, Feb. 1997.
[24] G. Gramegna, A. Magazzu, G. Sclafani and M.Paparo, “Ultra-wide dynamic range 1.75 dB noise-figure, 900 MHz CMOS LNA”, IEEE International Solid-State Circuits Conference, 2000. Digest of Technical Papers, pp. 380-381, Feb. 2000
[25] H. Samavati, H. R. Rategh and T. H. Lee, “A 5-GHz CMOS Wireless LAN Receiver Front End”, IEEE J. Solid-State Circuits, Vol. 35, No. 5, pp. 765-772, May 2000.