臺灣博碩士論文加值系統

本論文提出了一裝置在輸電網路中之測距電驛(阻抗電驛)偵測三相平衡故障發生位置的一近似方法，並且分析在三種輸電網路模型中測距電驛所能保護到的區域範圍，再者配合FPGA設計完成以此近似法則為基礎之數位式測距電驛。最後以靈敏度法則討論接地阻抗、電源比例常數等對於電驛端阻抗值之效應，並進而修正誤差值，以獲得精確判斷故障位置之能力。
本文最主要分為兩大研究方向，第一為使用MATLAB分析輸電網路中的電力潮流，而後當輸電線上不同位置發生故障時，計算電驛端的故障電壓、電流，進而得到阻抗值。分析與模擬不同故障位置所獲得的阻抗值，可進而建立故障點阻抗與電驛端阻抗的關係圖，進而規劃出故障點區域範圍。往後當輸電線上有故障發生時，就可得知此故障點是落於哪一個區域範圍之內。再者，本論文利用Xilinx 公司開發的XC2s200 FPGA晶片及雅普科技所開發與FPGA相關的週邊，以Verilog硬體描述語言撰述數位式測距電驛相關功能，配合Xilinx ISE軟體，完成電驛功能的合成、驗証、模擬、埠指定，及下載等步驟，達到數位式電驛的設計目標。最後與傳統式電驛之功能比較，証明本論文提出的設計的確較傳統式電驛功能優異。

This thesis proposes an approximated method to simulate and design the functions of distance relay (impendence relay) to efficiently detect the three-phase balanced fault on the transmission line, as well as to analyze the reach of digital distance relay in three types of power system models. Based on the proposed methodology, the FPGA technique is applied to design and implement the digital distance relay. Finally, a sensitivity analysis is applied to discuss the effect of grounding impedance, voltage source ratio to the value of relay terminal impedance and then the modified error is introduced to improve the ability of fault location detection.
There are two purposes in this thesis. The first purpose of this thesis is to utilize the MATLAB package to run the power flow and fault calculation to obtain the parameters of voltage, current and then impedance at relay location with respect to different faulted located along the transmission line. Based on the simulation results, the relationship between relay measured impedance and faulted location (impedance) can easily be established. Several extreme cases in different faulted location are simulated to establish the exact protection area. In the case of occurring faults on transmission line, the proposed approach can efficiently detect the fault situation and can estimate the faulted location. The second purpose of this thesis is to apply FPGA XC2s200 chip and their peripheral produced by Xilinx corp. and local Zeppe corp. respectively to finish the design procedures of synthesis, justification, simulation, pin assignment, generating program, and program download for FPGA. Finally the verification for the FPGA design shows that the better performance and the effectiveness of the proposed methodology can be achieved.

中文摘要 -----------------------------------------------------i
ABSTRACT ----------------------------------------------------ii
誌謝 ----------------------------------------------------iv
目錄 ---------------------------------------------------vii
表目錄 ----------------------------------------------------ix
圖目錄 ----------------------------------------------------xi
符號說明 ---------------------------------------------------xiv
第一章 緒論-------------------------------------------------1
1.1 研究動機與背景---------------------------------------1
1.2 研究目標及方法---------------------------------------3
1.3 相關研究概況-----------------------------------------4
1.4 內容大綱---------------------------------------------8
第二章 測距電驛理論-----------------------------------------9
2.1 基本概念---------------------------------------------9
2.2 具有方向辨識能力的測距電驛--------------------------10
2.3 測距電驛之保護有效範圍------------------------------13
2.4 理論推演--------------------------------------------16
第三章 FPGA應用在測距電驛的設計----------------------------23
3.1 FPGA基本觀念----------------------------------------23
3.1.1 FPGA硬體電路設計規則--------------------------------26
3.2 Verilog硬體描述語言---------------------------------29
3.2.1 Verilog語言的特性與傳統數位電路設計的優缺點比較-----31
3.3 以FPGA進行距離偵測法則------------------------------34
3.3.1 片段線性內差法--------------------------------------35
3.3.2 以片段線性內差法求解故障位置------------------------36
第四章 模擬系統設計----------------------------------------39
4.1 模擬系統設備----------------------------------------39
4.2 研究方法規劃----------------------------------------41
4.3 模擬軟體設計----------------------------------------43
第五章 模擬結果與分析--------------------------------------53
5.1 MALAB模擬結果與分析---------------------------------53
5.1.1 測距電驛敏感度分析結果------------------------------79
5.2 FPGA設計結果與分析----------------------------------81
5.2.1 以FPGA設計測距電驛保護區間--------------------------88
第六章 結論與未來展望--------------------------------------91
6.1 結論------------------------------------------------91
6.2 未來展望--------------------------------------------93
參考文獻 ----------------------------------------------------95
附錄一 MATLAB模擬測距電驛功能之數據-----------------------103

[1] P. Gallagher, V. Chickermane, S. Grego, and T. S. Pierre,“A building block BIST methodology for SOC designs: A case study,” in Proc. IEEE Int. Test Conf., Baltimore, MD USA, pp.111-120, Oct. 30-Nov. 1, 2001.
[2] R. A. Bergamaschi and W. R. Lee, “Designing systems-on-chip using cores,” in Proc. IEEE 37th Design Automation Conf., pp. 420-425, June 5-9, 2000.
[3] E.J. Marinissen et al., “On IEEE P1500’s standard for embedded core test,” IEEE Trans. on Electronic Testing, vol. 18, pp. 365-383, Aug. 2002.
[4] Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Krasniewski, and Gopind N. Kumar, “Design and optimization of multi-level TAM architectures for hierarchical SOCs,” in Proc. IEEE 21th VLSI Test Symposium, pp. 299-304, Apr. 27-May 1, 2003.
[5] 譚旦旭, 曾國雄, 工業配電, 四版七刷, 台北：高立圖有限公司, 1998.
[6] Glover and Sarma, 電力系統設計與分析, 黃文良, 二版四刷, 台北：全華科技圖書股份有限公司, 1998.
[7] Chul-Hwan Kim, Myung-Hee Lee, Raj K. Aggarwal, and Allan T. John, “Educational use of EMTP models for the study of a distance relaying algorithm for protecting transmission lines,” IEEE Trans. on Power System, vol. 15, no. 1, pp. 9-15, Feb. 2000.
[8] 曾國雄, 林家任, 高文秀, “負載模型對測距電驛特性之分析”, 中華民國第二十二屆電力工程研討會, 高雄, 台灣, pp. 229-233, 11月 22-23, 2001.
[9] Y. L. Li, B. Li , X. H. Zhang, and J. L. He, “An ANN-BASED distance protective relays of transmission lines,” in Proc. IEE Developments in Power System Protection 7th Int. Conf., Amsterdam Netherlands, pp. 311-314, Apr. 9-12, 2001.
[10] Tarlochan S. Sidhu, Daljit S. Ghotra, and Mohindar S. Sachdev, “An adaptive distance relay and its performance comparison with a fixed data window distance relay,” IEEE Trans. on Power Delivery, vol. 17, no. 3, pp. 691-693, July 2002.
[11] Mattias Jonsson and Jaap Daalder, “Distance protection and voltage stability,” in Proc. IEEE Power System Technology Int. Conf., pp. 971-976, Dec. 4-7, 2000.
[12] Zhang Guiqing, Feng Tao, Wang Jianhua, Zhang Hang, Xu Hong, Geng Yinsan, and Zheng Shiquan, “The SOC design and implementation of digital protective relay based on IP cores,” in Proc. IEEE Power System Technology Int. Conf., pp. 2580-2583, Oct. 13-17, 2002.
[13] Feng Tao, Zhang Guiqing, Wang Jianhua, Geng Yingsan , and Zhang Hang, “A FPGA-BASED implementation of data acquisition and processing for digital protective relays,” in Proc. IEEE ASIC 4th Int. Conf., pp. 518-521, Oct. 23-25, 2001.
[14] M. Claus, S. Lemmer, and G. Ziegler, “Proceedings in distance relaying,” in Proc. IEE Developments in Power System Protection 6th Int. Conf., Nottingham, UK, pp. 28-31, March 25-27, 1997.
[15] Y. Q. Xia, K. K. Li, and A.k. David, “Adaptive relay setting for stand-alone digital distance protection,” IEEE Trans. on Power Delivery, vol. 9, no. 1, pp. 480-491, Jan. 1994.
[16] Chang-Ho Jung, Dong-Joon Shin, and Jin-O Kim, “Adaptive setting of digital relay for transmission line protection,” in Proc. IEEE Power System Technology Int. Conf., pp.1465-1468, Dec. 4-7, 2000.
[17] Zhang Zhizhe and Chen Deshu, “An adaptive approach in digital distance protection,” IEEE Trans. on Power Delivery, vol. 6, no. 1, pp. 135-142, Jan. 1991.
[18] 鄭信源, Verilog硬體描述語言數位電路設計實務, 一三版, 台北：儒林圖書有限公司, 2003.
[19] Members of the Power Systems Relaying Committee of the IEEE, IEEE recommended practice for protection and coordination of industrial and commercial power systems, USA: Industrial and Commercial Power Systems Committee of the IEEE Industry Applications Society, 1991.
[20] F. M. Abouelenin and H. M. Jabr, “Behavior study of polarized distance relay in presence of the simultaneous faults,” in Proc. IEEE 11th Mediterranean Electrotechnical Conference, pp. 517-521, May 7-9, 2002.
[21] J. B. Lee, C. H. Jung, I. D. Kim, and Y. K. Baek, “Protective relay testing and characteristic analysis for high impedance faults in transmission lines,” in Proc. IEEE Power Engineering Society Summer Meeting, Edmonton, Alta. Canada, pp. 1076-1081, July 18-22, 1999.
[22] D. L. Waikar, S. Elangovan, and A. C. Liew, “Fault impedance estimation algorithm for digital distance relaying,” IEEE Trans. on Power Delivery, vol. 9, issue 3, pp. 1375-1383, July 1994.
[23] K. K. Li, L. L. Lai, and A. K. David, “Stand alone intelligent digital distance relay,” IEEE Trans. on Power Systems, vol. 15, no. 1, pp. 137-142, Feb. 2000.
[24] K. R. Cho, Y. C. Kang, S. S. Kim, J. K. Park, S. H. Kang, and K. H. Kim, “An ANN based approach to improve the speed of a different equation based distance relaying algorithm,” IEEE Trans. on Power Delivery, vol. 14, no. 2, pp. 349-357, Apr. 1999.
[25] M. S. Sachdev and M. A. Baribeau, “A new algorithm for digital impedance relays,” IEEE Trans. on Power Apparat. Syst., vol. PAS-98, pp. 2232-2240, Nov. 1979.
[26] 謝佳銘, “嵌入式SOC-Based監控系統之設計與實現,” 碩士論文, 國立成功大學, 中華民國, 2001.
[27] H. S. Gill, T. S. Sidhu, and M. S. Sachdev, “Microprocessor-based busbar protection system,” IEE Proc. on Gener. Transm. Distrib., vol. 147, issue 4, pp. 252-260, July 2000.
[28] S. Toral, J. M. Quero, and L. G. Franquelo, “Power energy metering based on random signal processing (EC-RPS),” in Proc. IEEE Circuit and Systems Int. Symposium, pp. 435-438, May 31-June 3, 1998.
[29] Pierre J. Bricaud, “IP reuse creation for system-on-a-chip design,” in Proc. IEEE Custom Integrated Circuit Conf., San Diego, CA USA, pp. 395-401, May 16-19, 1999.
[30] Yunsi Fei and Niraj K. Jha, “Functional partitioning for low power distributed systems of systems-on-a-chip,” in Proc. IEEE 15th International Conference on VLSI Design(VLSID’02), Bangalore, India, pp. 247-281, Jan. 7-11, 2002.
[31] R. P. Dick and N. K. Jha, “MOCSYN: Multiobjective core-based single-chip system synthesis,” in Proc. IEEE Design Automation and Test in Europe Conf., Munich, Germany, pp. 263-270, Mar. 9-12, 1999.
[32] D. D. Gajski, F. Vahid, S. Narayan, and J. Gong, Specification and design of embedded systems, NJ: Prentice-Hall Englewood Cliffs, 1994.
[33] B. Gold and C.M. Rader, Digital processing of signals, New York: McGraw-Hill, 1969.
[34] Yu Guangzong, Progress and interface of ASIC, Microelectronic technology, 1999.
[35] M. S. Sachdev and T. S. Sidhu, “Modelling relays for use in power system protection studies,” in Proc. IEE Developments in Power System Protection 7th Int. Conf., Amsterdam, Netherlands, pp. 523-526, Apr. 9-12, 2001.
[36] Mahmoud A. Manzoul, “Overcurrent relay on a FPGA chip,” IEEE Trans. on Microelectron Reliability, vol. 35, no. 7, pp. 1017.-1022, July 1995.
[37] T. S. Sidhu, M. S. Sachdev, and R. Das, “Modern relays: Research and teaching using PCs,” IEEE Trans. on Comput. Appl. Power, vol. 10, issue 2, pp. 50-57, Apr. 1997.
[38] S. H. Horowitz, A. G. Phadke, and J. S. Thorpe, “Adaptive transmission system relaying,” IEEE Trans. on Power Delivery, vol. 3, issue 4, pp. 1436-1445, Oct. 1988.
[39] A. K. Jampala, S. S. Venkata, and M. J. Damborg, “Adaptive transmission protection: Concepts and computational issues,” IEEE Trans. on Power Delivery, vol. 4, no. 1, pp. 177-185, Jan. 1989.
[40] G. D. Rockefeller, C. L. Wagner, and J. R. Linders, “Adaptive transmission relaying concepts for improved performance,” IEEE Trans. on Power Delivery, vol. 3, no. 4, pp. 1446-1458, Oct. 1998.
[41] W. A. Elmore, Protective relaying: Theory and application, Marcel Dekker. Inc., 1994.
[42] R. E. Ray and H. J. Li, “A computer—directed model power system,” Western Protective Relaying Conference, Spokane, Washington, USA, pp. 256-259, Oct. 21-23, 1986.
[43] D. L. Waikar, A. C. Liew, and S. Elangovan, “Design, implementation and performance evaluation of a new digital distance relaying algorithm,” IEEE Trans. on Power System, vol. 11, issue 1, pp. 448-456, Feb. 1996.
[44] A. S. AlFuhaid and M. A. El-Sayed, “A recursive least-squares digital distance relaying algorithm,” IEEE Trans. on Power Delivery, vol. 14, issue 4, pp. 1257-1262, Oct. 1999.
[45] Samir Palnitkar, Verilog硬體描述語言, 黃英叡、黃稚存、張銓淵、江文啟，初版四刷, 台北市：全華科技圖書股份有限公司, 2002.
[46] E. D. Lagnese and D. E. Thomas, “Architectural partitioning for system level synthesis of integrated circuits,” IEEE Trans. on Computer-Aided Design, vol. 10, no. 7, pp. 847-860, July 1991.
[47] A. A. Duncan, D. C. Hendry, and P. Gray, “An overview of the COBRA-ABS high level synthesis system for multi-FPGA systems,” in Proc. IEEE FPGAs for Custom Computing Machines Conf., Napa Valley, CA USA, pp. 106-115, Apr. 15-17, 1998.
[48] Xilinx Inc. Research Group, Xilinx data book, Xilinx Inc., 2002.
[49] 雅普科技研究團隊, Xilinx XC2S200數位整合發展系統使用手冊, 新竹：雅普科技有限公司, 2003.
[50] P. J. Moore and A.T. Johns, “Adaptive digital distance protection,” in Proc. IEE Developments in Power Protection 4th Int. Conf., Edinburgh, UK, pp. 187-191, Apr. 11-13, 1989.
[51] J. B. Lee, C. W. Ha, and C. H. Jung, “Development of digital distance relaying algorithm in combined transmission lines with underground power cables,” in Proc. IEEE Power Engineering Society Summer Meeting, Vancouver, BC Canada, pp. 611-616, July 15-19, 2001.
[52] G. B. Gilcrest, G. D. Rockefeller, and E. A. Udren, “High speed distance relaying using a digital computer─part I: System description,” IEEE Trans. on Power Apparat. Syst., vol. PAS-91, pp.1235-1243, Nov. 1972.
[53] Zhang Guiqing , Feng Tao, Zhang Hang, Wang Jianhua, XuHong, Geng Yingsan , and Zheng Shiquan, “The implementation of digital protection in power system using FPGA,” in Proc. IEEE 4th International Conference on ASIC, Shanghai, China, pp. 474-477, Oct. 23-25, 2001.
[54] A. G. Phadke and J. S. Thorp, Computer relaying for power systems, New York: Wiley, 1998.
[55] G. Nimmersjo, Q. Werner-Erichsen, B. Hillstrom , and G. D. Rockefeller, “A digitally-controlled, real-time, analog power-system simulator for closed-loop protective relaying testing,” IEEE Trans. on Power Delivery, vol. 3, issue. 1, pp. 138-152, Jan. 1988.
[56] M. S. Sachdev, Advancements in microprocessor—based protection and communication, NJ: IEEE Press. Tutorial Cource Text Piscataway, 1997.
[57] G. Ziegler, “Actual development, manufacturing and testing experiences with microprocessor based system protection,” in Proc. IEEE/NTUA Power Tech. Conf., Athens, Greece, pp. 315-320, Sep. 5-8, 1993.
[58] H. Hupfauer, G. Koch, M. Mainka, and H. P. Michaelis, “Management and service experience with numerical relays in transmission systems,” CIGRE Conference, Paris, France, pp. 34-108, May 5-7, 1992.
[59] Liancheng Wang and Elmo Price, “New high-speed microprocessor distance relaying for transmission lines,” in Proc. IEEE Power System Technology (POWERCON ''98) Int. Conf., Beijing, China, pp. 1143-1147, Aug. 18-21, 1998.
[60] B. R. J. Caunce, “Digital protection for power systems [book reviews],” IEE Power Engineering Journal, vol. 10, issue 1, pp. 3, Feb. 1996.
[61] A. T. Johns and R. K. Aggarwal, “Digital simulation of faulted E.H.V transmission lines with particular reference to very-high-speed protection,” IEE Proc. Pt.C, vol.123, no.4, pp.353-359, Apr. 1976.
[62] F. Calero, “Development of a numerical comparator for protective relaying: part I,” IEEE Trans. on Power Delivery, vol. 11, no. 3, pp. 1266-1273, July. 1996.
[63] M. A. Manzoul, “Multi-function protective relay on FPGA,” IEEE Trans. on Microelectron Reliability, vol. 38, no. 12, pp. 1963-1968, Dec. 1998.
[64] Marcello Lajolo et. al., “Cosimulation-based power estimation for SOC Design,” IEEE Trans. on VLSI System, vol. 10, no. 3, pp. 253-366, June 2002.