臺灣博碩士論文加值系統

在此篇論文中，我們使用金屬鈦摻雜於高介電材料二氧化鋯可以得到較大的介電常數及較佳的特性。此絕緣層經過快速熱退火處理後可以修補絕緣層的缺陷並且改善絕緣層品質，進而使元件特性獲得改善。
另一方面，使用二氧化鋯當做快閃記憶體的電荷儲存層。由結果得之，在經過800度快速熱退火後，擁有最佳的電性表現。二氧化鋯作為電荷儲存層有著可接受1.87V的記憶儲存範圍、較快的寫入與抹除速度、較佳的電荷保留能力與耐用性。此外我們也使用鈦摻雜二氧化鈰作為電荷儲存層，在900度亦可得到較佳的電荷儲存特性。
最後，我們研究在P型基板上成長碳參雜應變矽的應變碳化矽結構，然後沉積三氧化二鋱於應變碳化矽上，並研究其電性與物性。由結果得知，經過800度的快速熱退火會有最佳的電性表現。

In this thesis, the Ti-doped high-k ZrO2 material has larger dielectric constant and better characteristics. The RTA annealing process can repair the oxide defect and obtain a stronger bonding to improve the device characteristics.
On the other hand, ZrO2 material was used as charge storage layer in flash memory. In our result, the ZrO2 material has better characteristics after annealing treatment at 800℃. The ZrO2 as charge storage layer has a memory window of 1.87 V, higher P/E speed, better data retention and superior endurance characteristics. In addition, we also use Ti-doped CeO2 material as charge storage layer and it shows better electrical characteristic at 900℃annealing.
Finally, we study the Tb2O3 dielectric deposited on the strained-Si with in situ carbon incorporation (st-Si:C) grown on the p-type silicon substrate. The physical and electrical characteristics of Tb2O3 materials were investigated. In our result, the Tb2O3 dielectric deposited on the st-Si:C with RTA 800℃has better performance.

Content
指導教授推薦書
口試委員審定書
論文著作授權書
Acknowledgement…………………………………………………….. iv
Chinese abstract……………………………...……………....v
English abstract…………………………… ..….... vi
Content..………………...………………..……...…..vii
Content of Figure.…………………………………....xi

Chapter 1 Introduction
1.1 General Background ………..………………...………………...........1
1.1.1 Study of the strain Si applied to the channel……………….......1
1.1.2 Study of Non-volatile Memories……………………………….2
1.1.3 Study of using high-k materials………………………………...3
1.2 The motivation in this study ………………………………………...4
1.3 Thesis Organization………………………………………………….5

Chapter 2 Electrical and Physical Characteristics of the High-k Tb2O3 (Terbium) Dielectric Deposited on The Strained-Si:C/p-type Si
2.1 Introduction ………………………………………..………………...7
2.2Experimental……..………….............………………………….....8
2.3 Analysis of Physical Characteristics
2.3.1XRD of Tb2O3 film after post-RTA annealing on the strained-Si:C/p-type silicon substrate……………………….. 9
2.3.2 X-ray photoelectron spectroscopy (XPS) of analysis for Tb2O3 film after post-RTA treatment……………………………… 10

2.3.3 Atomic force microscope (AFM) of analysis for Tb2O3 film after post-RTA treatment…………………………………… 12
2.4 Analysis of Electrical Characteristics…………………………...13
2.5 Summaries…………………………….….………..........................14

Chapter 3 The comparison of Electrical and Physical Characteristics between ZrO2and ZrTiO4
3.1 Introduction ……………………………….…………….………….24
3.2 Experimental………...……….……………..….…….....................25
3.3 Analysis of Physical Characteristics
3.3.1-1 XRD of ZrO2 film after post-RTA annealing at various temperatures……………………………………………………27
3.3.1-2 XRD of ZrTiO4 film after post-RTA annealing at various temperatures……………………………………………………28
3.3.2-1 X-ray photoelectron spectroscopy (XPS) of analysis for ZrO2 film after post-RTA treatment……………………………….. 28
3.3.2-2 X-ray photoelectron spectroscopy (XPS) of analysis for ZrTiO4 film after post-RTA treatment……………………….. 30
3.3.3-1 Atomic force microscope (AFM) of analysis for ZrO2 film after post-RTA treatment……………………………………….32
3.3.3-2 Atomic force microscope (AFM) of analysis for ZrTiO4 film after post-RTA treatment……………………………………….32
3.4 Analysis of Electrical Characteristics
3.4-1 Electrical Characteristic of the ZrO2 sample………………….33
3.4-2 Electrical Characteristic of the ZrO2 sample………………….35
3.5 Summary…………………………………………………………….36

Chapter 4 The ZrO2 Trapping Layer in Flash Memory Applications
4-1 Introduction……………………………………….…….……..........55
4-2 Experimental………….…………………………………….………56
4.3 Analysis of Physical Characteristics
4.3.1 XRD of ZrO2 trapping layer after post-RTA annealing at various temperatures................................................................ 57
4.3.2 XPS of ZrO2 trapping layer after post-RTA annealing at various temperatures................................................................57
4.3.3 AFM of ZrO2 trapping layer after post-RTA annealing at various temperatures………………………………………....59
4.4 Analysis of Electrical Characteristics
4.4.1 Hysteresis of ZrO2 trapping layer after post-RTA annealing at various temperatures………………………………………….59
4.4.2 Program/Erase speed of ZrO2 trapping layer after post-RTA annealing at various temperatures……………………......…..60
4.4.3 Retention and endurance of ZrO2 trapping layer after post-RTA annealing at various temperatures………………...………….61
4-5 Summaries…………………………………………………………..62

Chapter 5 The Ce2TiO5 Trapping Layer in Flash Memory Applications
5.1 Introduction …………………………….…………….…………….77
5.2 Experimental…………..……….……………..….…….....................78
5.3 Analysis of Physical Characteristics
5.3.1 XRD of Ce2TiO5 trapping layer after post-RTA annealing at various temperatures................................................................ 79
5.3.2 XPS of Ce2TiO5 trapping layer after post-RTA annealing at various temperatures............................................................... 79
5.3.3 AFM of Ce2TiO5 trapping layer after post-RTA annealing at various temperatures………………………………………... 81
5.4 Analysis of Electrical Characteristics
5.4.1 Hysteresis of Ce2TiO5 trapping layer after post-RTA annealing at various temperatures……………………………………….82
5.4.2 Program speed of Ce2TiO5 trapping layer after post-RTA annealing at various temperatures……………..……………..83
5.4 Summaries………………………………….…….……....................83

Chapter 6 Conclusions and Future Work
6-1 Conclusion …………….....…….…………………….….………...97
6.1.1 Electrical and Physical Characteristics of the high-k Tb2O3 (Terbium) Dielectric Deposited on The Strained-Si:C/p-type Si………………..………………………………………….....97
6.1.2 The comparison of electrical and physical characteristics between ZrO2 and ZrTiO4………………..………………..97
6.1.3 The ZrO2 and Ce2TiO5 trapping layer in flash memory applications……………………………………...…….……98
6-2 Future work………………………………………………………...98

References …………………………………………..……...……….....99

Content of Figure
Chapter 1
Fig. 1 Desired stress on CMOS performance.
Chapter 2
Fig. 2-1 The Al/Tb2O3/st-Si:C/ p-type silicon capacitor structure.
Fig. 2-2 XRD results of Tb2O3 film after post-RTA annealing from 600oC to 8000C in N2 ambient for 30 sec.
Fig. 2-3 XPS results of (a) Tb 4d, (b) O 1s and (c) C 1p Tb2O3 film after post-RTA annealing at various temperatures from 600 to 8000C in N2, 30 sec.
Fig. 2-4 AFM images of Tb2O3 surface of the (a) as–deposited sample and the samples treated at RTA (b) 6000C, (c) 7000C, and (d) 800oC in N2, 30 sec.
Fig. 2-5 AFM images of st-Si:C surface of the (a) as–deposited sample and the samples treated at RTA (b) 6000C, (c) 7000C, and (d) 800oC in N2, 30 sec.
Fig. 2-6 The I-V characteristics of the as–deposited sample and the samples at various RTA temperatures from 600 to 8000C under the top gate applied with(a) positive bias and (b)negative bias.
Fig. 2-7 The gate voltage shift versus time for the as–deposited sample and the samples at various RTA temperatures from 600 to 8000C under the constant current stress with (a) positive current stress and (b) negative current stress.

Chapter 3
Fig. 3-1 (a) The ZrO2 capacitor structure.
Fig. 3-1 (b) The ZrTiO4 capacitor structure.
Fig. 3-2 XRD of the ZrO2 film after annealing at various temperatures.
Fig. 3-3 XRD of the ZrTiO4 film after annealing at various temperatures.
Fig. 3-4 (a) XPS of Zr 3d for ZrO2 trapping layer after RTA annealing treatment at various temperatures.
Fig. 3-4 (b) XPS of O 1s for ZrO2 trapping layer after RTA annealing
treatment at various temperatures.
Fig. 3-4 (c) XPS of Si 2p for ZrO2 trapping layer after RTA annealing
treatment at various temperatures.
Fig. 3-5 (a) XPS of Zr 3d for ZrTiO4 trapping layer after RTA annealing treatment at various temperatures.
Fig. 3-5 (b) XPS of Ti 2p for ZrTiO4 trapping layer after RTA annealing treatment at various temperatures.
Fig. 3-5 (c) XPS of O 1s for ZrTiO4 trapping layer after RTA annealing
treatment at various temperatures.
Fig. 3-5 (d) XPS of Si 2p for ZrTiO4 trapping layer after RTA annealing
treatment at various temperatures.
Fig. 3-6 AFM images on high-k surface of ZrO2 films after PDA at different temperatures.
Fig. 3-7 Surface roughness of ZrO2 trapping layer after RTA annealing treatment at various temperatures.
Fig. 3-8 AFM images on high-k surface of ZrTiO4 films after PDA at different temperatures.
Fig. 3-9 Surface roughness of ZrTiO4 trapping layer after RTA annealing treatment at various temperatures.
Fig. 3-10 C-V curves of ZrO2 capacitor after annealing at various temperatures.
Fig. 3-11 C-V curves of ZrTiO4 capacitor after annealing at various temperatures.
Fig. 3-12 The J-E characteristics of the ZrO2 after annealing at various temperature under the top gate applied with positive bias.
Fig. 3-13 The J-E characteristics of the ZrTiO4 after annealing at various temperature under the top gate applied with a positive bias.
Fig. 3-14 The J-E characteristics of the ZrO2 after annealing at various temperature under the top gate applied with a negative bias.
Fig. 3-15 The J-E characteristics of the ZrTiO4 after annealing at various temperature under the top gate applied with a negative bias.
Fig. 3-16 The gate voltage shift versus time of the ZrO2 for the as–deposited sample and the samples with post-RTA treatment at various temperatures from 600ºC to 900ºC (a) positive constant current (+ 5μA/cm2) stress and (b) negative constant current (-5μA/cm2) stress.
Fig. 3-17 The gate voltage shift versus time of the ZrTiO4 for the as–deposited sample and the samples with post-RTA treatment at various temperatures from 600ºC to 900ºC (a) positive constant current (+ 5μA/cm2) stress and (b) negative constant current (-5μA/cm2) stress.


Chapter 4
Fig. 4-1 Process flow and capacitor structures of Al/SiO2/ZrO2/SiO2/Si.
Fig. 4-2 XRD of the ZrO2 film after annealing at various temperatures
Fig. 4-3 (a) XPS of Zr 3d for ZrO2 trapping layer after RTA annealing
treatment at various temperatures.
Fig. 4-3 (b) XPS of O 1s for ZrO2 trapping layer after RTA annealing treatment at various temperatures.
Fig. 4-3 (c) XPS of Si 2p for ZrO2 trapping layer after RTA annealing treatment at various temperatures.
Fig. 4-4 AFM images on high-k surface of ZrO2 films after PDA at different temperatures in N2 ambient for 30s.
Fig. 4-5 Surface roughness of ZrO2 trapping layer after RTA annealing treatment at various temperatures.
Fig. 4-6 (a) Hysteresis properties of Al/SiO2/ ZrO2/SiO2/Si structures for as-deposited.
Fig. 4-6 (b) Hysteresis properties of Al/SiO2/ ZrO2/SiO2/Si structures for annealed at 600℃ in N2 for 30s.
Fig. 4-6 (c) Hysteresis properties of Al/SiO2/ ZrO2/SiO2/Si structures for annealed at 700℃ in N2 for 30s.
Fig. 4-6 (d) Hysteresis properties of Al/SiO2/ ZrO2/SiO2/Si structures for annealed at 800℃ in N2 for 30s.
Fig. 4-6 (e) Hysteresis properties of Al/SiO2/ZrO2/SiO2/Si structures for annealed at 900℃ in N2 for 30s.

Fig. 4-7 Programming speed of Al/SiO2/ ZrO2/SiO2/Si structures for annealed at 700℃ and 800℃ in N2 for 30s.
Fig. 4-8 (a) Erasing speed of Al/SiO2/ ZrO2/SiO2/Si structures for annealed at 700℃in N2 for 30s.
Fig. 4-8 (b) Erasing speed of Al/SiO2/ ZrO2/SiO2/Si structures for annealed at 800℃in N2 for 30s.
Fig. 4-9 Retention characteristic of Al/SiO2/ZrO2/SiO2/Si structures for
RTA 700℃and 800℃treatment and measured at 25℃ and 85℃.
Fig. 4-10 Endurance of Al/SiO2/ ZrO2/SiO2/Si structures for annealed at 800℃ in N2 for 30s.
Chapter 5
Fig. 5-1 Process flow and capacitor structures of Al/SiO2/Ce2TiO5/SiO2/Si.
Fig. 5-2 XRD of the Ce2TiO5 film after annealing at various temperatures.
Fig. 5-3 (a) XPS of Ce 3d for Ce2TiO5 trapping layer after RTA annealing
treatment at various temperatures.
Fig. 5-3 (b) XPS of Ti 2p for Ce2TiO5 trapping layer after RTA annealing treatment at various temperatures.
Fig. 5-3 (c) XPS of O 1s for Ce2TiO5 trapping layer after RTA annealing treatment at various temperatures.
Fig. 5-3 (d) XPS of Si 2p for Ce2TiO5trapping layer after RTA annealing treatment at various temperatures.
Fig. 5-4 AFM images on high-k surface of Ce2TiO5 films after RTA at different temperatures in N2 ambient for 30s.

Fig. 5-5 Surface roughness of Ce2TiO5 trapping layer after RTA annealing treatment at various temperatures.
Fig. 5-6 (a) Hysteresis properties of Al/SiO2/ Ce2TiO5/SiO2/Si structures for as-deposited.
Fig. 5-6 (b) Hysteresis properties of Al/SiO2/ Ce2TiO5/SiO2/Si structures for annealed at 700℃ in O2 for 30s.
Fig. 5-6 (c) Hysteresis properties of Al/SiO2/ Ce2TiO5/SiO2/Si structures for annealed at 800℃ in O2 for 30s.
Fig. 5-6 (d) Hysteresis properties of Al/SiO2/ Ce2TiO5/SiO2/Si structures for annealed at 900℃ in O2 for 30s.
Fig. 5-6 (e) Hysteresis properties of Al/SiO2/ Ce2TiO5/SiO2/Si structures for annealed at 950℃ in O2 for 30s.
Fig. 5-7 Programming speed of Al/SiO2/ ZrO2/ Ce2TiO5/Si structures for annealed at 800℃ and 900℃ in O2 for 30s.

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