臺灣博碩士論文加值系統

由於浮動式閘極快閃記憶體無法滿足元件微縮發展的趨勢，因此利用電荷陷阱式快閃記憶體式取代浮動式閘極結構元件是未來發展的趨勢。然而傳統SONOS元件以氮化矽做為電荷儲存層的結構，在發展到次微米以下時就無法再以降低穿隧氧化層厚度的方式來提升元件操作效率，因此便引進了高介電材料來取代傳統ONO結構以提升元件操作機制。而在通道介面處磊晶一層矽化鍺或純鍺，藉由能帶工程提升操作載子的能量，希望藉此材料的應用達到較高的元件操作效率。
比較矽化鍺、純鍺通道中，藉由調變不同的單晶矽覆蓋層厚度，改善矽化鍺、純鍺通道與穿隧氧化層之間的界面特性，探討對於TAHOS元件的效率影響。 比較矽化鍺、純鍺通道中，藉由調變不同的溫度，觀察鍺原子受到溫度的影響所對元件產生的效應，探討對於TAHOS元件的效率影響。利用不同的方法達到高濃度矽化鍺或純鍺結晶層，探討不同方法對於高濃度矽化鍺與純鍺結晶層的優缺點。
而經由實驗結果發現，單晶矽覆蓋層的選擇是非常重要的，些微的厚度都會影響寫入、抹除與電荷保持的特性。不同的退火溫度會直影響元件的寫入、抹除與電荷保持的特性(在低鍺含量的矽化鍺通道元件中，不易觀察到)。利用乾式氧化達成高鍺含量的矽化鍺薄膜其結晶狀況雖佳，但是表面粗糙度很差，不適合使用其結果製作元件，而使用超晶格所製作出來的純鍺薄膜，則擁有良好的結晶狀況與良好的表面粗糙度，是未來做為純鍺通道的良好方法。

Abstract
Charge-trapping (CT) flash is regarded as one of the most promising nonvolatile memory devices. Some approaches were proposed to further enhance the operation properties of CT flash devices by stacked high-k charge-trapping layer , stacked tunneling oxides with thicker physic thickness , metal gate with high work function, and SiGe buried channel(small band gap) .
SiGe and Ge buried channel with different annealing temperature and various thicknesses of Si-cap layer on operation characteristics of charge-trapping (CT) flash devices were studied in this work. And We use different method to formation of high concentration SiGe layer or crystalline Ge layer.
We can have 5 Conclusions, 1. Programming and erasing speeds of all samples with SiGe buried channel are faster than control sample.2. The thickness of Si-cap would affect the properties of programming and retention obviously.3. For deuces with pure Ge channel , lower annealing temperature should be better for the electrical properties of devices.4. The roughness of condensed SiGe layer would be a serious issue for the device fabrication.5. Good crystalline structure and low roughness SL layer would be a good buffer layer for the growth of crystalline Ge layer.

第一章序論 1
1.1 前言 1
1.2 快閃記憶體面臨問題 1
1.3 電荷陷阱式快閃記憶體的結構及其優缺點 2
1.4 研究目的 5
1.5 各章摘要 6
第二章快閃記憶體元件操作方法 13
2.1 寫入與擦拭方法 13
2.1.1 CHEI通道熱電子注入寫入 13
2.1.2 CHISEL初始通道載子引發二次電子注入寫入 14
2.1.3 BBHE帶對帶穿隧引發熱電子寫入 14
2.1.4 FN穿隧寫入 15
2.1.5 FN穿隧抹除 16
2.2 耐力 16
2.3 干擾 17
2.4 電荷保持 18
第三章實驗規劃及元件製程 30
3.1 實驗規劃 30
3.2電容元件製程 31
3.2.1 電容前段製程 31
3.2.2 矽化鍺通道磊晶製程 32
3.2.3 成長穿隧氧化層 32
3.2.4 沉積電荷儲存層以及阻擋層 32
3.3.5 電容後段製程 33
第四章 矽化鍺與鍺通道中調變不同單晶矽覆蓋層厚度對電荷陷阱式快閃記憶體特性影響 41
4.1 研究背景與目的 41
4.2 實驗規劃及製程 42
4.3 實驗結果與討論 43
4.3.1不同單晶矽覆蓋層厚度對於Ge30% 200Å通道的效應 43
4.3.1.1 不同單晶矽覆蓋層厚度對於Ge30% 200Å通道的寫入效應比較 44
4.3.1.2 不同單晶矽覆蓋層厚度對於Ge30% 200Å通道的抹除效應比較 45
4.3.1.3 不同單晶矽覆蓋層厚度對於Ge30% 200Å通道的電荷保持效應比較 46
4.3.2 不同單晶矽覆蓋層厚度對於Pure-Ge 200Å通道的效應比較 47
4.3.2.1 不同單晶矽覆蓋層厚度對於Pure-Ge 200Å通道的寫入效應比較 47
4.3.2.2 不同單晶矽覆蓋層厚度對於Pure-Ge 200Å的通道的抹除效應比較 49
4.3.2.3 不同單晶矽覆蓋層厚度對於Pure-Ge 200Å的通道的電荷保持效應比較 51
4.4 結論 52
第五章 矽化鍺與鍺通道中經不同退火溫度對電荷陷阱式快閃記憶體特性影響 70
5.1 研究背景與目的 70
5.2 實驗規劃及製程 71
5.3 實驗結果與討論 72
5.3.1不同退火溫度對於Ge11% 200Å的通道的效應 72
5.3.1.1不同退火溫度對於Ge11% 200Å的通道的寫入效應比較 72
5.3.1.2不同退火溫度對於Ge11% 200Å的通道的抹除效應比較 73
5.3.1.3對於Ge11% 200Å的通道不同退火溫度的電荷保持效應比較 74
5.3.2不同退火溫度對於PURE-GE 200Å的通道的效應 75
5.3.2.1不同退火溫度對於Pure-Ge 200Å的通道的寫入效應 75
5.3.2.2不同退火溫度對於Pure-Ge 200Å的通道的抹除效應 76
5.3.2.3不同退火溫度對於Pure-Ge 200Å的通道的電荷保持效應 78
5.4結論 79
第六章高濃度矽化鍺結晶方法之探討 91
6.1高濃度矽化鍺結晶原理 91
6.1.1使用乾式氧化達到高濃度矽化鍺結晶 92
6.1.2利用氫氣退火改善表面粗糙度 92
6.1.3利用超晶格的堆疊達到結晶的純鍺層 93
6.2實驗規劃及製程 93
6.2.1 實驗規劃 93
6.2.2實驗製程 94
6.3實驗結果與討論 94
6.3.1矽化鍺(鍺含量30%)之乾式氧化結晶方法探討 94
6.3.1.1 矽化鍺(鍺含量30%)之乾式氧化結晶製作流程 94
6.3.1.2矽化鍺(鍺含量30%)之乾式氧化結晶之探討 95
6.3.2 超晶格(多層的Ge/Si)之結晶方法 97
6.3.2.1超晶格(多層的Ge/Si)之結晶製程 97
6.3.2.2超晶格(多層的Ge/Si)之結晶探討 97
6.3.2.3退火製程對於超晶格(多層的Ge/Si) 之影響 100
6.4結論 100
第七章 結論與建議 138
7.1 結論 138
7.2 建議 139

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