臺灣博碩士論文加值系統

世界十大死因的前兩名分別為心血管疾病與腦血管疾病，此已成為不可忽視的重要問題。而往往這些疾病的診治需要長時間的監控其相關生理訊號，如心電圖、腦電圖等，而為了提高監控的效率，需要一個輕薄方便攜帶，且低功率消耗與高解析度的無線生理訊號檢測系統。
本論文所實現的生理訊號檢測類比前端電路則是為了能達到上述目標所提出，並且不同於傳統的生理訊號檢測系統，本論文提出一應用在無線傳輸檢測系統上，能更簡化其電路設計的架構，並且定義生理訊號頻寬為200 Hz，整體系統有效位元數為12位元，功率消耗約為28.5μW。電路實現部分則是採用TSMC 0.18μm 1P6M製程實現一個類比前端電路架構，其中包含截波穩定型前置放大器與三階Feedforward架構的高通三角積分調變器，其系統量測結果顯示SFDR為72dB。供應電壓為1.2V，總功率消耗則為28.5μW。

The ones of the top ten causes of the death in the world are including Ischaemic heart disease as well as Stroke and other cerebrovascular disease. However, the diagnosis of disease usually requires long time to monitor the related bio-signals, eg. EEG or ECG. A wireless biomedical signal acquisition systems with low power consumption and high resolution is necessary for monitoring effectively and carrying conveniently.
In this thesis, an analog front end circuit for wireless biomedical signal acquisition systems is implemented. Different from the tradition acquisition systems, the proposed analog front end circuit with a signal bandwidth of 200 Hz, Effective number of bits ( ENOB) of 12 bits is simpler to save on the power consumption.
The circuits with chopper stabilization preamplifier and high-pass sigma-delta modulator are implemented in TSMC 0.18μm 1P6M CMOS process. The measured results reveal the SFDR is 72dB.The total power consumption is 28.5μW under the supply voltage of 1.2V.

致謝 i
中文摘要 ii
Abstract iii
目錄 iv
圖目錄 viii
表目錄 xii
第1章 緒論 1
1.1研究動機 1
1.2章節規劃 3
第2章 應用於無線生理訊號檢測類比前端電路系統架構比較與探討 5
2.1 傳統應用在無線生理訊號檢測系統類比前端電路系統 架構 5
2.2 應用於無線生理訊號檢測系統類比前端電路系統架構 6
第3章 截波穩定前置放大器的分析與設計 9
3.1 CMOS雜訊來源 9
3.1.1 雜訊頻譜 9
3.1.2 熱雜訊(thermal noise) 10
3.1.3 閃爍雜訊(flicker noise) 11
3.2 雜訊處理相關技術 12
3.2.1 自動歸零(Autozero,AZ)技術 12
3.2.2 相關性雙取樣(Correlated Double Sampling,CDS)技術 13
3.2.3 截波穩定(Chopper Stabilization,CHS)技術 13
3.3 截波穩定技術介紹與分析 14
3.3.1 基本原理介紹 14
3.3.2 放大器有限頻寬對截波穩定技術的影響 16
3.3.3 白色雜訊調變 17
3.3.4 閃爍雜訊調變 17
3.4 截波調變器的非理想特性 18
3.4.1 時脈饋入(Clock Feedthrough) 18
3.4.2 通道電荷注入(Channel Charge Injection) 19
3.4.3 殘餘偏壓(Residual Offset) 20
3.5截波穩定型差動差分放大器分析 21
3.5.1 差動差分放大器架構 22
3.5.2 差動差分放大器頻率響應分析 22
3.5.3差動差分放大器共模拒斥比 25
3.5.4差動差分放大器雜訊分析 26
3.6截波穩定型差動差分放大器電路實現 29
3.6.1 差動差分放大器頻率響應 29
3.6.2 前置放大器模擬結果 32
3.6.3 截波穩定型前置放大器 36
第4章 高通三角積分調變器的分析與設計 42
4.1 量化雜訊(Quantization Noise) 42
4.2 效能指標 45
4.2.1 解析度 45
4.2.2 訊號雜訊比 45
4.2.3 訊號雜訊與失真比 45
4.2.4 動態範圍 45
4.3 超取樣技術 46
4.3.1超取樣的概念 47
4.4 雜訊整型 48
4.4.1 一階雜訊整型 51
4.4.2 二階雜訊整型 53
4.4.3 高階雜訊整型 54
4.5 自動合成係數工具 56
4.6 系統規格 57
4.6.1 架構選用 57
4.6.2 效能模擬 58
4.7 高通三角積分調變器的非理想效應 60
4.7.1 運算放大器的有限增益與增益的非線性之影響 60
4.7.2 熱雜訊之影響 64
4.7.3 係數變異量之影響 65
4.8 高通三角積分調變器電路實現 65
4.8.1 電容切換式積分器 66
4.8.2 增益的非線性度 69
4.8.3 開關的雜訊分析 70
4.8.4 高通三角積分調變器電路 71
4.8.5 比較器 76
4.8.6 時脈訊號產生器 76
4.9 高通三角積分調變器電路模擬結果 77
4.10 類比前端電路系統佈局與模擬 79
4.10.1 佈局考量 79
4.10.2 模擬結果 81
第5章 量測考量與結果 84
5.1 量測環境的建立 84
5.1.1 差動差分放大器頻率響應 84
5.1.2 截波穩定型前置放大器功率頻譜密度分析 84
5.1.3類比前端系統功率頻譜密度量測 85
5.1.4 PCB板照相圖 86
5.2 量測結果 87
5.2.1 差動差分放大器頻率響應 87
5.2.2 截波調變器功率頻譜密度 89
5.2.3差動差分放大器功率頻譜密度 90
5.2.4前置放大器功率頻譜密度 91
5.2.5 高通三角積分調變器頻譜密度 92
5.2.6類比前端電路功率頻譜密度 93
5.3 文獻比較 96
5.4 總結 97
第6章 結論與未來規畫 99
6.1 結論 99
6.2 未來規畫 99
6.1.1 右腳驅動電路 99
6.1.2 電極貼片所產生的誤差 101
參考文獻 102

[1] Top ten causes of death by broad income group (2008). World health organization. Retrieved Oct.18, 2011. From http://www.who.int/mediacentre/factsheets/fs310/en/index.html
[2] L. S. Y. Wong, et. al, “A very low-power CMOS mixed-signal IC for implantable pacemaker applications,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2446–2456, Dec. 2004.
[3] L. S. Y. Wong et al., “A very low power CMOS mixed-signal IC for implantable pacemaker applications,” in Proc. IEEE Solid State Circuits Conf., Feb. 2004, pp. 318–319.
[4] J. G. Webster, Medical Instrumentation, application and design, 4th ed. NJ: Wiley, 2008.
[5] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization,” Proc. IEEE, vol. 84, no. 11, pp. 1584–1614, Nov. 1996.
[6] S. Y. Lee, Y. C. Su, M. C. Liang, J. H. Hong, C. H. Hsieh, C. M. Yang, Y. Y. Chen, H. Y. Lai, J. W. Lin, Q. Fang, “A programmable implantable micro-stimulator SoC with wireless telemetry: Application in closed-loop endocardial stimulation for cardiac pacemaker,” in Proc. IEEE Solid State Circuits Conf., Feb. 2011, pp. 44 – 45.
[7] X. D. Zou, X. Y. Xu, L. B. Yao, and Y. Lian, “A 1V 450nW Fully Integrated Programmable Biomedical Sensor Interface System,” IEEE J. Solid-State Circuits, vol. 44, No.4, pp. 1067-1077, Apr. 2009.
[8] R. F. Yazicioglu, P. Merken, R. Puers, C. Van Hoof, “A 200μW Eight-Channel EEG Acquisition ASIC for Ambulatory EEG systems,” IEEE J. Solid-State Circuits, vol. 43, No. 12, pp. 3025 -3038, Dec. 2008.
[9] N. Verma, A. Shoeb, J. Bohorquez, J. Dawson, J. Guttag, A.P. Chandrakasan, “ A Micro-Power EEG Acquisition SoC with Integrated Feature Extraction Processor for a Chronic Seizure Detection System,” IEEE J. Solid-State Circuits, vol. 45, No. 4, pp. 804-816, Apr. 2010.
[10] R. F. Yazicioglu, P. Merken, R. Puers, and C. V. Hoof, “A 60 μW 60nV/√Hz readout front-end for portable biopotential acquisition systems,” IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1100–1110,May 2007.
[11] T. Denison, K. Consoer, W. Santa, A. Avestruz, J. Cooley, and A. Kelly, “2μW 100nV/√Hz chopper stabilized instrumentation amplifier for chronic measurement of neural field potentials,” IEEE J. Solid-State Circuit, vol. 42, no. 12, pp. 2934–2945, Dec. 2007.
103
[12] B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2005.
[13] Y. P. Tsivids, Operation and Modeling of the MOS Transistor. New York: McGraw-Hill, 1987.
[14] A. M. Abo and P. R. Gray, “A 1.5-V 10-bit 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 34, pp.599–606, May 1999.
[15] D. A Johns, K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc 1997.
[16] S. Y. Lee, “Switched-Current IC Design and Bandpass Sigma-delta Modulator Structure Synthesis, ” Ph.D thesis, 1999,NCKU.
[17] T. H. Kuo, K. D. Chen, and J. R. Chen, “Automatic Coefficients Design for High-order Sigma-delta Modulators, ” IEEE Trans. Circuits Syst. II, Analog and Digital Signal Processing, vol. 46, no. 1,pp. 6-15, Jan. 1999.
[18] K. D. Chen, “Automatic Coefficient Synthesis and Circuit Implementation Techniques of High Order Sigma-Delta Modulators, ” Ph.D thesis, 2000, NCKU.
[19] F. Medeiro, B. Perez-Verdu, A. Rodriguez-Vazquez, and J. L. Huertas,“Modeling opamp-induced harmonic distortion for switched-capacitor sigma-delta modulator design,” IEEE Proc. ISCAS ’94, vol. 5, London, U.K., May 1994, pp. 445–448.
[20] V. T. Nguyen, P. Loumeau, J. F. Naviner, “VHDL-AMS behavioral modeling and simulation of high-pass delta-sigma modulator,” Behavioral Modeling and Simulation Workshop, 2005, pp. 106 -111.
[21] S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-sigma data converters, in Theory, Design and Simulation. (Piscataway, NJ: IEEE Press, 1997).
[22] R. Schreier, G. C. Temes, “Understanding Delta-Sigma Data converter, ” pp. 307 IEEE PRESS, New York.
[23] M. Mollazadeh, K. Murari, G. Cauwenberghs, N. Thakor, “Micropower CMOS Integrated Low noise Amplification, Filtering, and Digitization of Multimodal Neuropotentials,” IEEE Trans. Biomedical Circuit and Systems, vol. 3, No. 1, pp. 1-10, Feb. 2009
[24] B. Winter and J. Webster, “Driven-right-leg circuit design,” IEEE Trans. Biomed. Eng., vol. 30, pp. 62–66, Jan. 1983.
[25] B. B. Winter and J. G. Webster, "Reduction of interference due to common mode voltage in biopotential amplifiers," IEEE Trans. Biomed. Eng., vol. 30, pp. 58-62, Jan. 1983.
[26] E. M. Spinelli, et al., “A Transconductance Driven-Right-Leg Circuit”, IEEE Transaction on Biomedical Engineering, Vol. 46, No.12, pp. 1466-1470, Dec.
104
1999
[27] R. F. Yazicioglu, P. Merken, and C. Van Hoof, “Effect of electrode offset on the CMRR of current balancing instrumentation amplifiers,” Ph.D. Res. Microelec. Elec. (PRIME), vol. 1, pp. 35–38, Jul. 2005.
[28] J. Xu, R. F. Yazicioglu, P. Harpe, K. A. A. Makinwa and C. Van Hoof, “A 160μW 8-channel active electrode system for EEG monitoring”, in Proc. IEEE Solid State Circuits Conf. , Feb. 2011, pp. 300-301.
[29] Q. Fan et al., “A 1.8μW 1μV-Offset Capacitively-Coupled Chopper Instrumentation Amplifier in 65nm CMOS”, in Proc. ESSCIRC, 2010, pp. 170-173.