臺灣博碩士論文加值系統

本論文提出一個十二位元每秒二十億次取樣之電流源式數位類比轉換器設計，解決三個主要的非線性度來源，分別是電流源不匹配、輸出轉換非線性度及有限輸出阻抗，並達到高速高解析的特性。首先，對於電流源不匹配，隨機旋轉式二元權重選取和資料權重平均化這兩種不同的動態元件匹配演算法被採用來針對不同的應用降低不匹配誤差造成的諧波失真。其次，對電流單元採取減少電流開關及非疊接的調整來提升輸出轉換速度並降低轉換非線性度的影響。除此之外，採用重置式的數位歸零技術以進一步增加輸出轉換線性度。最後，對於有限輸出阻抗的問題，提出一個輸出阻抗補償電路來補償電流單元的非線性阻抗曲線。透過解決這些非線性度的來源，此數位類比轉換器在高取樣速率下仍表現優異。
此電流源式數位類比轉換器之實現是採用TSMC 90奈米，1P9M互補金氧半導體製程，主動電路面積僅0.07平方毫米。量測結果顯示，此數位類比轉換器可達到在十億赫茲取樣頻率下從低頻到四億赫茲的SFDR均大於70dB，且效能指數和世界頂尖的作品相比均為最佳。

In this thesis, a 12-bit 2GS/s current-steering DAC design is presented to overcome the three main nonlinearity sources, which are current source mismatch, output transition nonlinearity, and finite output impedance, and achieve high-speed high-resolution characteristic. Firstly, for the current source mismatch, two different dynamic element matching (DEM) algorithms, random rotation-based binary-weighted selection (RRBS) and data weighted averaging (DWA), are adopted to process the harmonic distortion tones caused by mismatch error for different applications. Secondly, reduced-switch and non-cascoded modifications of the current cells increase the output transition speed and decrease the influence of transition nonlinearity. In addition, a digital resetting return-to-zero (RTZ) is adopted to further enhance the output transition linearity. Finally, for the finite output impedance, an output impedance compensation circuit is proposed to compensate the nonlinear impedance curve of current cells. By dealing with these nonlinearity sources, this DAC performs excellent at high sampling rate.
The current-steering DAC is fabricated in TSMC 90nm 1P9M CMOS technology with only 0.07mm2 of active area. The measurement results show that the DAC achieves 〉70dB SFDR from dc to 400MHz sampling at 1GHz and performs best in figure of merit (FOM) comparing to state-of-the-art works.

摘要 I
Abstract II
Acknowledgements III
Table of Contents IV
List of Tables VII
List of Figures VIII
Chapter 1: Introduction 1
1.1 Motivation 1
1.2 Organization 3
Chapter 2: Fundamental of Nyquist-Rate DAC 4
2.1 Ideal DAC 5
2.2 Static Performances 6
2.3 Dynamic Performances 10
2.4 Zero-Order Hold Response 15
2.5 Architecture of Digital-to-Analog Converters 16
2.5.1 Resistor-String Based DAC 16
2.5.2 Binary-Weighted Resistor DAC 19
2.5.3 Charge-Redistribution DAC 23
2.5.4 Current-Steering DAC 24
Chapter 3: Techniques for Linearity Enhancement 25
3.1 Suppression of Mismatch Effect 26
3.1.1 Current Source Mismatch Effect 27
3.1.2 Dynamic Element Matching (DEM) 31
3.2 Reduction of Output Transition Nonlinearity 37
3.2.1 Acceleration of Output Transition Speed 37
3.2.2 Digital Resetting Return-to-Zero 42
3.3 Compensation of Finite Output Impedance 45
3.3.1 The Parallel Connection Effect 45
3.3.2 Output Impedance Compensation 48
Chapter 4: Circuit Design and Implementation 51
4.1 Circuit Design Details 51
4.1.1 Build-in Testing Circuits 53
4.1.2 DEM Algorithm 55
4.1.3 Switch Driver 56
4.1.4 Current Cell Array 58
4.1.5 Output Impedance Compensation Circuits 61
4.1.6 Clock Receiver and Buffer 64
4.2 Pre-layout Simulation Results 66
4.2.1 Intrinsic DAC 66
4.2.2 Current Cell with Reduced Current Switch 67
4.2.3 Current Cell without Cascode Transistor 68
4.2.4 Return-to-Zero Circuit 70
4.2.5 Output Impedance Compensation Circuit 71
4.3 Layout and Post-layout Simulation Results 73
4.3.1 Circuit Layout and Consideration 73
4.3.2 Simulation Results 76
4.3.3 Performance Summary and Comparison to State-of-the-Art 79
Chapter 5: Performance Measurements 81
5.1 Measurement Setup 81
5.2 PCB Design Consideration 82
5.3 Measurement Results 85
5.4 Performance Summary and Comparison 90
Chapter 6: Conclusion and Future Work 94
Reference 96

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