臺灣博碩士論文加值系統

隨著摩爾定律（ Moore’s Law ）繼續成立，可同時執行的應用程式的數量持續增長，對主記憶體的容量需求也繼續增加當中。近年來，學者們致力於研究能比動態隨機存取記憶體（ DRAM ）提供更大容量、更低耗電的記憶體技術。其中，具有非揮發性及極佳的製程微縮性的相變化記憶體（ PCM，phase-change memory ）被視為是取代DRAM 的最佳候選。然而，相變化記憶體仍存在一些需被克服的缺點。例如，它的寫入速度比起動態隨機存取記憶體慢得許多，進而成為相變化主記憶體系統的效能障礙。
在本篇論文，我延伸前一文獻所提出，已證實可彌補相變化記憶體之較差效能之「多項目窄列緩衝區相變化記憶體組織」（ multiple narrow row buffer organization for PCM ）。我提出兩個「列緩衝區管理策略」（ row buffer management policy ），及兩個「記憶體庫間平行存取方案」（ intra-bank parallelism scheme ）來更加利用多項目窄列緩衝區之效能潛力。實驗模擬顯示列緩衝區管理策略對於記憶體密集之工作負載具有平均2.27% 及最大2.51% 之系統效能提昇，而記憶體庫間平行存取方案對於記憶體密集之工作負載具有最大67.5% 之系統效能提昇。另外，記憶體庫間平行存取方案對於較不記憶體密集之工作負載亦有最大12%的系統效能提昇。

As Moore’s Law continues to hold true, the number of concurrently running applications has been increasing, and the capacity requirement of main memory has been much aggravated. For recent years, researchers have been studying new memory technologies that are envisioned to provide more memory capacity and lower power than the conventional DRAM. Among them, phase-change memory (PCM) has been considered as the best candidate to replace DRAM as main memory due to its non-volatility, byte-addressability, and superior scalability. Nevertheless, there have still been a number of drawbacks of PCM that need to be addressed in order to enjoy the full benefit of it. For example, the write latency of PCM is much longer than that of DRAM, which often poses as a performance bottleneck for PCM-based main memory system.
In this thesis, I extend one previous work that proposed the multiple narrow row buffer organization for PCM, which was reported to be effective in mitigating the relatively poor performance of PCM; I propose two row buffer management policies and two intra-bank parallelism schemes to exploit the full potential of such organization. Simulation shows that the proposed row buffer management policies bring an average of 2.27% and a maximum of 2.51% performance improvement, and that the proposed intra-bank parallelism schemes bring a maximum of additional 67.5% performance improvement for memory intensive workloads. Moreover, intra-bank parallelism schemes are observed to provide a maximum of 12% performance improvement for less memory intensive workloads.

Acknowledgments i
摘要 ii
Abstract iii
1 Introduction 1
2 Background and Related Works 4
2.1 Phase-Change Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Memory Structures and Accesses . . . . . . . . . . . . . . . . . . . . 6
2.3 Multiple Row Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Mechanisms 11
3.1 Row Buffer Management Policies . . . . . . . . . . . . . . . . . . . . 11
3.1.1 Clean-First Least-Recently Used (CFLRU) row buffer replacement
policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.2 Early Write-Back (EWB) . . . . . . . . . . . . . . . . . . . . . 13
3.2 Intra-Bank Parallelism Schemes . . . . . . . . . . . . . . . . . . . . . 14
3.2.1 Concurrent Row Buffer Accesses (CRB) . . . . . . . . . . . . 14
3.2.2 Concurrent Data Sensing and Programming (CSP) . . . . . . 17
4 Experimental Methodology 20
5 Experimental Results 23
5.1 High-MPKIWorkload Mixes . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1 Row Buffer Management Policies . . . . . . . . . . . . . . . . 24
5.1.2 Intra-Bank Parallelism Schemes . . . . . . . . . . . . . . . . . 26
5.2 Medium- and Low-MPKI Workload Mixes . . . . . . . . . . . . . . 32
5.2.1 Row Buffer Management Policies . . . . . . . . . . . . . . . . 32
5.2.2 Intra-Bank Parallelism Schemes . . . . . . . . . . . . . . . . . 36
6 Conclusions 41
Bibliography 43

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