臺灣博碩士論文加值系統

60G 寬頻無線通訊系統需要一個快速的 ADC(4-7 bits)。Flash ADC 被用在許多高速產品像收音機、光通訊、光學讀取頭和超寬頻無線接收器。本論文提出一個應用於高速的六位元動態折疊式快閃式類比數位轉換器設計。利用折疊把傳統快閃式類比數位轉換器所需的比較器數目大大減少，因此可以降低功率，且只消耗動態功率又不需校正的省電類比數位轉換器。並為了消除製程變異造成的誤差，我們採用電阻平均技術。
本晶片使用台積電 90-nm CMOS 製程製作，根據量測結果，本晶片在1GHz的轉換頻率下的DNL和INL分別為-0.6/+0.8LSB和-0.6/+0.8LSB，在輸入頻率為9.99MHz且工作在80MHz的轉換頻率下時，量測到的SNDR和SFDR分別為33.74dB和49.93dB，當輸入頻率為466.544MHz且工作在1GHz的轉換頻率時，其SNDR和SFDR分別為30.07dB和37.19dB，操作在1.2伏特電壓時功率消耗為25mW，全部的晶片面積大小為0.46mm^2，然而主動電路所占的面積只有0.07mm^2。

Communication in the unlicensed frequency band around 60GHz requires a very fast ADC with low resolution (4-7 bits). Flash ADC offers the highest sampling rate, which is adapted in these high speed applications such as radio astronomy, optical communication, magnetic and optical read channels, and ultra-wideband wireless receivers. In this paper, we propose a high-speed Dynamic Folding Flash A/D Converter. Use of folding the traditional flash analog to digital converter comparator required substantially reduce the number, it can reduce the power, dynamic power consumption and does not need calibration type analog to digital converter. To alleviate random offset caused by process variation, resistive averaging technique is adopted.
This ADC is demonstrated in a standard 90-nm CMOS process. According to the measurement results, the prototype ADC exhibits a DNL of -0.6/+0.8LSB and an INL of -0.6/+0.8LSB at the sampling rate of 1GS/s. With 9.99MHz input frequency, the SNDR and SFDR achieve 33.74dB and 49.93dB at 80MS/s. The SNDR and SFDR are 30.07dB and 37.19dB at 1GS/s in 466.544MHz input frequency. The power consumption is 25mW at 1.2V supply. The active area is 0.07mm^2and whole chip with pads occupies 0.46mm^2.

Table of Contents
致謝 ................................................... I
摘要 .................................................. II
Abstract ............................................. III
Table of Contents ..................................... IV
List of Tables ......................................... X
Chapter 1 .............................................. 1
Introduction ........................................... 1
1.1 Motivation ......................................... 1
1.2 Thesis Organization ................................ 2
Chapter 2 .............................................. 4
Fundamentals of Analog-to-Digital Converters ........... 4
2.1 Introduction ....................................... 4
2.2 Performance Metrics ................................ 4
2.2.1 Offset and Gain Error ............................ 4
2.2.2 Differential and Integral Nonlinearity (DNL, INL). 4
2.2.3 Signal-to-Noise Ratio (SNR) ...................... 6
2.2.4 Total Harmonic Distortion (THD) .................. 7
2.2.5 Spurious-Free Dynamic Range (SFDR) ............... 7
2.2.6 Signal-to-Noise and Distortion Ratio (SNDR) ...... 8
2.2.7 Effective Number of Bits (ENOB) .................. 8
2.2.8 Figure of Merit (FoM) ............................ 9
2.3 Architecture of Analog-to-Digital Converters ....... 9
2.3.1 Flash ADC ........................................ 9
2.3.2 Two-Step ADC .................................... 11
2.3.4 Folding ADC ..................................... 12
2.3.5 Pipelined ADC ................................... 14
2.3.4 Successive-Approximation ADC .................... 15
2.4 Summary ........................................... 17
Chapter 3 ............................................. 18
Proposed architecture ................................. 18
3.1 Introduction ...................................... 18
3.2 Propose ADC Architecture .......................... 19
3.2.1 Timing .......................................... 21
3.2.2 CFs Transfer Function ........................... 23
Chapter 4 ............................................. 25
Circuit Implementation and Simulation Results ......... 25
4.1 CFs ............................................... 25
4.2 CADC and FADCs .................................... 31
4.3 Dynamic averaging network ......................... 32
4.4 Dynamic comparator latch .......................... 38
4.5 Digital error correction .......................... 39
4.6 Clock Generator ................................... 41
4.7 Simulation Results ................................ 43
4.7.1 Charge Folding (CF) Gain ........................ 43
4.7.2 The offset effect of Dynamic Average network .... 44
4.7.3 Simulated Result with Ramp Input ................ 44
4.7.4 DNL and INL Simulation .......................... 45
4.7.5 FFT Simulation .................................. 45
4.8 Summary ........................................... 47
Chapter 5 ............................................. 49
Test Setup and Measurement Results .................... 49
5.1 Introduction ...................................... 49
5.2 Floor Plan and Layout Considerations .............. 49
5.3 Test Setup ........................................ 50
5.4 PCB Design ........................................ 53
5.5 Experiment Results ................................ 57
5.5.1 Static Performance .............................. 60
5.5.2 Dynamic Performance ............................. 61
5.6 Summary ........................................... 64
Chapter 6 ............................................. 67
Conclusions ........................................... 67
Bibliography .......................................... 69

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