臺灣博碩士論文加值系統

可重組系統的快速發展，為嵌入式系統帶來了許多新的應用與挑戰．其中軟／硬體分割設計在整個可重組式系統規劃上為相當重要的課題．然而因為重組時間 (Reconfiguration time) 過長，因此應用中選擇利用可重組式硬體加速的部份將會受限．根據研究發現，若在軟／硬體分割 (HW/SW partitioning) 的過程中，考量降低可重組式硬體的重組負擔 (Reconfiguration overhead)，則應用中選擇利用可重組式硬體加速的部份將可增加．
　　在本論文中，我們探討如何降低重組負擔使得利用可重組式硬體的利益可以作更多的發揮．在軟／硬體分割時，我們提出了兩個方法，分別為：重疊微處理器的執行時間與重組時間以隱藏重組時間，以及合併組態以減少重組次數．此外，在軟／硬體分割後，再次的合併經過軟／硬體分割後決定由可重組式硬體執行部份的組態，進一步的減少需要重組的次數．並且利用Mediabench作為實驗對象來顯示我們方法的效能．

摘要…………………………………………………………………………………….i Abstract………………………………………………………………………………..ii 誌 謝………………………………………………………………………………iii Table of Contents……………………………………………………………………iv List of Figures………………………………………………………………………..vi List of Tables………………………………………………………………………....vii
Chapter 1 Introduction………………………………………………………………...1
1.1 HW/SW partitioning for Reconfigurable System……………………………2
1.2 Motivation……………………………………………………………………3
1.3 Objective and Proposed mechanism…………………………………………4
1.4 Organization of This Thesis………………………………………………….4
Chapter 2 Background and Related Works……………………………………………6 2.1 Run-Time Reconfigurable (RTR) System…………………………………....6 2.1.1 Definition……………………………………………………………..6 2.1.2 HW/SW partitioning on RTR System………………………………...7 2.2 Configuration Prefetch……………………………………………………….7 2.2.1 Prefetching Factor…………………………………………………….7 2.2.2 Cost Function…………………………………………………………9 2.3 Loop Unrolling for Reconfigurable Computing…………………………….11 2.4 Operator Parallelism Exploration within Loops on Reconfigurable Hardware…………………………………………………………………..12
2.4.1 Term Definitions……………………………………………………..12 2.4.2 Overall Approach……………………………………………………13 Chapter 3 Design of HW/SW Partitioning and HW Configuration Determination.....15
3.1 Design Flow.…………………………………………………………….....15 3.1.1 Term Definitions……………………………………………………..16 3.2 Procedure of HW/SW Partitioning………………………………………….18
3.2.1 Rule 1: Compare the Reconfiguration Time with The Benefit Gained by Using RH instead of µP………………………………………………...18 3.2.2 Rule 2: Configuration Prefetch……………………………………...19 3.2.3 Rule 3: Configuration Merge………………………………………..24
3.3 Rules of HW Configuration Determination………………………………...29
3.3.1 Merge in The Same Block…………………………………………...30
3.3.2 Merge between Different Blocks……………………………………30
3.4 Discussion of Merge and Unroll……………………………………………33 Chapter 4 Simulation Environment and Results……………………………………..36 4.1 Benchmark Suite…………………………………………………………....36 4.1.1 Criteria for Selecting Benchmarks…………………………………..36 4.1.2 Mediabench Benchmarks…………………………………………....37 4.2 Simulation Methods………………………………………………………...40 4.2.1 Simulation Tool……………………………………………………...40 4.2.2 Simulation Assumption……………………………………………...40 4.3 Simulation Results…………………………………………………………..40 4.3.1 Inner Loop Ratio…………………………………………………….41 4.3.2 Reduction of Execution Time………………………………………..42 Chapter 5 Conclusions and Future Works……………………………………………52

[1] Yanbing Li, Tim Callahan, Ervan Darnell, Randolph Harr, Uday Kurkure and Jon Stockwood “Hardware-Software Co-design of Embedded Reconfigurable Architectures” ACM 2000
[2] Adam Kaplan, Majid Sarrafzadef “A survey of Hardware/Software System Partitioning”
[3] W. Wolf. “Hardware/Software co-design of embedded systems” Proceedings of the IEEE, July 1994
[4] TSI Telsys, “ACE2 Card Manual” 1998
[5] Scott Hauck “Configuration Prefetch for Single Context Reconfigurable Coprocessors” ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 1999
[6] N. Ramasubramanian, R. Sunramanian, and S. Pande “Automatic Compilation of Loops to Exploit Operator Parallelism on Configurable Automatic Logic Units” IEEE transactions on Parallel and Distributed Systems, January 2002
[7] J Hauser, and J. Wawrzynek, “Garp: A MIPS Processor with a Reconfigurable Coprocessor” Proc IEEE Symp. FPGAs for Custom Computing Machines 1999
[8] Markus Weinhardt and Wayne Luk, Member, IEEE “Pipeline Vectorization” IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, February 2001
[9] http://www.xilinx.com/partinfo/databook.htm#xc4000
[10] Markus Weinhardt and Wayne Luk “Memory Access Optimization for Reconfigurable Systems” IEE Proc.-Comput. Digit. Tech. Vol. 148 No.3 May 2001
[11] C. Lee, M. Potkonjak, and W. H. M.-Smith, “MediaBench：A Tool for Evaluating and Synthesizing Multimedia and Communications Systems”, 30th Annual ACM/IEEE International Symposium on Microarchitecture, 1997.