透過鰭式場效電晶體(fin field-effect transistor, FinFET)元件的製作，可以有效地得到高密度、高性能與低成本的元件，已成為20nm製程下的新寵兒。FinFET結構中，在閘極門形成如魚鰭般的叉狀3D結構，可在電晶體的三側控制電路的開啟或關閉，加強閘極對通道的控制能力，並減少其漏電流與改善短通道效應。
利用90奈米的光罩與硬式遮罩的混合使用，可以製作成不同尺寸的p型FinFET元件。在本研究中，以固定通道寬度(W=0.11um)後，在各種不同通道長度(0.5um、2um及10um)進行量測，並比較單根與多根元件在各種不同通道長度下、溫度調變(25oC、75oC與125oC)與VT植入能量不同(20KeV與15KeV)時，對整體元件之效能影響作探討，分析其參數之差異，包括源/汲極電流、次臨界特性與臨界電壓等。
藉由實驗量測結果與分析得知，不論是在單根或多根通道之p型FinFET，在溫度效應下，尺寸較小的元件在驅動電流與臨界電壓上，都比尺寸較大的元件優異。在較高的植入能量優勢下，可獲得較高的驅動電流，乃其通道遷移率較高所貢獻的；另外，較低的植入能量，則可以得到較低些的臨界電壓，此乃整體之通道體濃度較淡些，通道反轉較容易，但較靠近通道表面，使得通道表面之散射會增加些，表現在次臨界擺幅與通道遷移率的值上。

Through the fabrication of fin field-effect transistors (FinFET), the IC products can be effectively promoted in the high density, the high performance and the low cost. In FinFET structure, it is similar to a 3-D profile with channel width providing the three-side controllability for the transistor device in switch, possibly reducing the current leakage and improving the short-channel effect.
Using a set of 90nm photo masks with the mixing application of hard mask, the p-type FinFETs can be fabricated out. In this research, measuring the tested devices and extracting the feasible parameters as the fixed channel width (W=0.11um) to probe the impact of different channel-length devices are the main tasks. The single and multiple-channel FinFETs with different channel lengths (0.5um, 2um and 10um) under temperature stress (25oC, 75oC and 125oC) are interestingly discussed as the VT adjustment energies (20KeV and 15KeV) were various. Employing these previous parameters in process and layout, the difference of the whole device performance in drive current, sub-threshold swing and threshold voltage can be distinguished well.
No matter what the single or multiple-channel p-type FinFET is, the smaller channel-length device shows the better drive current and the lower VT value than the larger one. In the higher VT implant energy, the drive current is higher due to the high contribution of the channel mobility. However, the lower VT implant energy proposes the lower VT value due to the lighter volume concentration in channel easily causing the channel inversion, but the scattering effect increases and the channel mobility decreases.

摘 要 i
Abstract ii
誌 謝 iii
目 錄 iv
表目錄 v
圖目錄 vi
第一章 緒論 1
1.1 簡介 1
1.2 研究動機 2
第二章 元件物理概念 3
2.1 半導體能帶(energy band)與能隙(energy gap)架構 3
2.2 p-n接面的結構與特性 4
2.3 內建電位與偏壓 6
2.4 電場分析與空乏區寬度 9
2.5 理想的MOS元件能帶圖 12
2.5.1 聚集 (accumulation) 12
2.5.2 空乏 (depletion) 13
2.5.3 反轉 (inversion) 13
2.6 金氧半場效電晶體之基本特性 14
2.7 理想MOSFET的I-V特性 16
2.8 IDS vs. VDS方程式的推導 17
2.9 轉移特性 (transfer characteristics) 19
2.10 其它重要元件參數 21
2.10.1 臨界電壓 (threshold voltage) 21
2.10.2 次臨界特性 (subthreshold characteristics) 22
2.10.3 遷移率退化 (mobility degradation) 24
2.10.4 基板偏壓效應 (body effect) 25
2.11 短通道效應 26
2.11.1 通道長度調變效應 (channel-length-modulation effect) 27
2.11.2 臨界電壓下滑 (threshold voltage roll-off) 29
2.11.3 汲極引起的能障下降 (drain-induced barrier lowering) 31
2.11.4 貫穿 (punch-through) 32
第三章 FinFET 35
3.1 鰭式場效電晶體 35
3.1.1 鰭式場效電晶體簡介 35
3.1.2 鰭式場效電晶體結構 36
3.1.3 鰭式場效電晶體製程 38
3.1.4 鰭式場效電晶體的優點與挑戰 39
3.2 SOI (silicon-on-insulator) 40
3.2.1 SOI的簡介 40
3.2.2 SOI晶圓的製作 41
3.2.3 SOI的特性 42
3.2.4 SOI元件的種類 42
第四章 實驗與結果 45
4.1 實驗量測架構說明 45
4.2 實驗機台簡介 46
4.2.1 手動探針量測平台(manual probe station) 46
4.2.2 半導體參數分析儀Agilent 4156C 47
4.2.3 Agilent E5250A 50
4.3 元件介紹 52
4.4 實驗條件 53
4.4.1 │ID│-VD特性曲線 53
4.4.2 │ID│-VG特性曲線 53
4.5 實驗結果 54
4.5.1 第一階段實驗結果 54
4.5.2 第二階段實驗結果 63
第五章 結論 72
參考文獻 74
作者簡介 78

[1]W.C. Lee, et al., “Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling,” IEEE Transactions Electron Devices, vol. 48, no. 7, pp. 1366-1373, July 2001.
[2]Q. Xie, et al., “Comprehensive analysis of short-channel effects in ultrathin SOI MOSFETs,” IEEE Transactions Electron Devices, vol. 60, no. 6, pp. 1814-1819, June 2013.
[3]T. Yamashita, et al., “Sub-25nm FinFET with advanced fin formation and short channel effect engineering,” IEEE VLSI Technology, pp. 14-16, June 2011.
[4]K. Roy, et al., “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits,” Proceedings of the IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.
[5]N. Yang, et al., “A comparative study of gate direct tunneling and drain leakage currents in n-MOSFET's with sub-2 nm gate oxides,” IEEE Transactions Electron Devices, vol. 47, no. 8, pp. 1636-1644, Aug. 2000.
[6]D. Hisamoto, et al., “FinFET-a self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Transactions Electron Devices, vol. 47, no. 12, pp. 2320-2325, Dec. 2000.
[7]X.J. Huang, et al., “Sub 50-nm FinFET: PMOS,” IEEE International Electron Devices Meeting (IEDM), pp. 67-70, Dec. 1999.
[8]J.D. Meindl, et al., “Beyond Moore's law: the interconnect era,” IEEE Computing in Science & Engineering, vol. 5, no. 1, pp. 20-24, Jan. 2003.
[9]劉傳璽、陳進來，“半導體元件物理與製程”，五南出版社，2011年。
[10]A.R. Brown, et al., “Impact of fermi level pinning at polysilicon gate grain boundaries on nano-MOSFET variability: A 3-D simulation study,” ESSDERC Solid-State Device Research Conference, pp. 451-454, Sept. 2006.
[11]Y. Murakami, et al., “Influence of film thickness on space charge formation under DC ramp voltage,” IEEE International Conference Solid Dielectrics (ICSD), pp. 448-451, June 2013.
[12]K. Uchida, et al., “Experimental study of biaxial and uniaxial strain effects on carrier mobility in bulk and ultrathin-body SOI MOSFETs,” IEEE International Electron Devices Meeting (IEDM), pp. 229-232, 13-15, Dec. 2004.
[13]T. Rudenko, et al., “Carrier mobility in undoped triple-gate FinFET structures and limitations of its description in terms of top and sidewall channel mobilities,” IEEE Transactions Electron Devices, vol. 55, no. 12, pp. 3532-3541, Dec. 2008.
[14]I.M. Filanovsky, et al., “Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits,” IEEE Circuits and Systems I: Fundamental Theory and Applications, vol. 48, no. 7, pp. 876-884, July 2001.
[15]Q. Chen, et al., “A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs,” IEEE Transactions Electron Devices, vol. 50, no. 7, pp. 1631-1637, July 2003.
[16]W.Y. Choi, et al., “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,” IEEE Electron Device Letters, vol. 28, no. 8, pp. 743-745, Aug. 2007.
[17]H.A. El Hamid, et al., “Analytical model of the threshold voltage and subthreshold swing of undoped cylindrical gate-all-around-based MOSFETs,” IEEE Transactions Electron Devices, vol. 54, no. 3, pp. 572-579, March 2007.
[18]S. Maeda, et al., “Substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel SOI MOSFET's,” IEEE Transactions Electron Devices, vol. 46, no. 1, pp. 151-158, Jan. 1999.
[19]H.S. Kang, et al., “Highly stable SOI technology to suppress floating body effect for high performance CMOS device,” IEEE International Electron Devices Meeting (IEDM), pp. 11.2.1-11.2.4, 2-5, Dec. 2001.
[20]Y. Dora, et al., “High breakdown voltage achieved on AlGaN/GaN HEMTs with integrated slant field plates,” IEEE Electron Device Letters, vol. 27, no. 9, pp. 713-715, Sept. 2006.
[21]G. Bersuker, et al., “Origin of the flatband-voltage roll-off phenomenon in metal/high-k gate stacks,” IEEE Transactions Electron Devices, vol. 57, no. 9, pp. 2047-2056, Sept. 2010.
[22]A. Aditya, et al., “Threshold voltage roll-off for triple gate FinFET analysis based on several semiconductors used as substrate,” IEEE International Conference High Performance Computing and Applications(ICHPCA), pp.1-6, Dec. 2014.
[23]H.W. Su, et al., “Drain-induced-barrier lowering and subthreshold swing fluctuations in 16-nm-gate bulk FinFET devices induced by random discrete dopants,” IEEE Device Research Conference, pp. 109-110, June 2012.
[24]A.A. Mutlu, et al., “Two-dimensional analytical model for drain induced barrier lowering (DIBL) in short channel MOSFETs,” Proceedings of the IEEE Southeastcon 2000, pp. 340-344, 2000.
[25]T. Matsudai, et al., “Advanced 60 μm thin 600 V punch-through IGBT concept for extremely low forward voltage and low turn-off loss,” IEEE International Symposium Power Semiconductor Devices and ICs (ISPSD), pp. 441-444, 2001.
[26]http://www.eetimes.com/document.asp?doc_id=1280773
[27]http://www.mem.com.tw/article_content.asp?sn=1402260021
[28]施敏、李明逵，“半導體元件物理與製作技術”，交通大學出版社，2013年。
[29]S. Flachowsky, et al., “Understanding strain-induced drive-current enhancement in strained-silicon n-MOSFET and p-MOSFET,” IEEE Transactions Electron Devices, vol. 57, no. 6, pp. 1343-1354, June 2010.
[30]鄭晃忠、劉傳璽，“新世代積體電路製程技術”，東華書局，2011年。
[31]Y. Tian, et al., “A novel nanoscaled device concept: quasi-SOI MOSFET to eliminate the potential weaknesses of UTB SOI MOSFET,” IEEE Transactions Electron Devices, vol. 52, no. 4, pp. 561-568, Apr. 2005.
[32]J.T. Park, et al., “Multiple-gate SOI MOSFETs: device design guidelines,” IEEE Transactions Electron Devices, vol. 49, no. 12, pp. 2222-2229, Dec. 2002.
[33]T. Mizuno, et al., “Electron and hole mobility enhancement in strained-Si MOSFET's on SiGe-on-insulator substrates fabricated by SIMOX technology,” IEEE Electron Device Letters, vol. 21, no. 5, pp. 230-232, May 2000.
[34]J. Kedzierski, et al., “Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation,” IEEE International Electron Devices Meeting (IEDM), pp. 247-250, Dec. 2002.
[35]A. Wei, et al., “Minimizing floating-body-induced threshold voltage variation in partially depleted SOI CMOS,” IEEE Electron Device Letters, vol. 17, no. 8, pp. 391-394, Aug. 1996.
[36]C. Zhao, et al., “16nm FinFETs with high-k last gate stack: processing challenges and solutions,” IEEE/EDSSC2014 in Chengdu, June 2014.
[37]W.S. Liao, et al., “Investigation of reliability characteristics in NMOS and PMOS FinFETs,” IEEE Electron Device Letters, vol. 29, no. 7, pp. 788-790, July 2008.
[38]W.S. Liao, et al., “Reliability investigation upon 30nm gate length ultra-high aspect ratio FinFETs,” Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International, pp. 541-544, Apr. 2005.
[39]M.C. Wang, et al., “Temperature stress probing performance of p-channel FinFETs under different VT implanting energies,” International Electron Devices and Materials Symposium (IEDMS), PID: 1226, Nov. 2014.
[40]M.C. Wang, et al., “Electrical characteristics of multi-gate p-channel FinFETs with VT implanting energies under temperature stress,” IEEE/ International Symposium on Next-Generation Electronics (ISNE), PID: 270159 (PW-16), May 2015.
[41]K. Martens, et al., “On the correct extraction of interface trap density of MOS devices with high-mobility semiconductor substrates,” IEEE Transactions Electron Devices, vol. 55, no. 2, pp. 547-556, Feb. 2008.
[42]E. Yoshida, et al., “A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory,” IEEE Transactions Electron Devices, vol. 53, no. 4, pp. 692-697, Apr. 2006.
[43]T. Ohtou, et al., “Impact of parameter variations and random dopant fluctuations on short-channel fully depleted SOI MOSFETs with extremely thin BOX,” IEEE Electron Device Letters, vol. 28, no. 8, pp. 740-742, Aug. 2007.
[44]T. Grasser, et al., “Switching oxide traps as the missing link between negative bias temperature instability and random telegraph noise,” IEEE International Electron Devices Meeting (IEDM), pp.1-4, Dec. 2009.
[45]Y. Wang, et al., “Random interface trap induced fluctuation in 22nm high-k/metal gate junctionless and inversion-mode FinFETs,” VLSI Technology Systems and Applications (VLSI-TSA), pp. 1-2, Apr. 2013.