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Chapter 1
[1-1] International Technology Roadmap for Semiconductors (ITRS), 2011, (http://www.itrs.net/Links/2011ITRS/Home2011.htm) [1-3] E. K. Lai, H. T. Lue, Y. H. Hsiao, J. Y. Hsieh, C. P. Lu, S. Y. Wang, L. W. Yang, T. Yang, K. C. Chen, J. Gong, K. Y. Hsieh, R. Liu, and C. Y. Lu, “Highly Scalable and Reliable Multi-bit/cell Nitride Trapping Nonvolatile Memory Using Enhanced ANS-ONO Process with A Nitridized Interface”, Tech. Dig. - Int. Electron Devices Meet. 2006, 1. [1-4] A. J. Walker, S. Nallamothu, E. H. Chen, M. Mahajani, S.B. Herner, M. Clark, J. M. Cleeves, S. V. Dunton, V.L. Eckert, J. Gu, S. Hu, J. Knall, M. Konevecki, C. Petti, S. Radigan, U. Raghuram, J. Vienna, and M. A. Vyvoda, “3D TFT-SONOS Memory Cell for Ultra-High Density File Storage Applications”, Tech. Dig. VLSI Technol. Symp. 2003, 29. [1-5] Adrian M. Ionescu, Heike Riel “Tunnel field-effect transistors as energy efficient electronic switches”, 17 NOVEMBER 2011, VOL 479, NATURE, 329 [1-6] A. S. Verhulst, W. G. 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M, “Pi-shape gate polycrystalline silicon thin-film transistor for nonvolatile memory applications”, Appl. Phys. Lett.2007 [1-16] Roberto Bez, Emilio Camerlenghi, Alberto Modelli, and Angelo Visconti “Introduction to Flash Memory”, Proc. IEEE 91, 489–502, 2003. [1-17] K. Kahng and S. Sze, “A floating gate and its application to memory devices”, IEEE Transactions on Electron Devices, vol. 14, pp. 629-629, 1967. [1-18] Frohman-Bentchkowsky, D.FAMOS, “A new semiconductor charge storage device”, Solid State Electronics. 17,517. 1974. [1-19] Harari E., Schmitz L., Troutman B., and Wang S., “A 256 bit nonovolatile static RAM”, IEEE ISSCC Tech. Dig., pp. 152, 1978.. [1-20] Kynett V.N., Baker A., Frandrich M., Hoekstra G.,Jungroth O., Kreifels J., and Wells S., “An in-system reprogrammable 256K CMOS Flash memory”, ISSCC Tec. Dig., pp.132, 1988. [1-21] Barbara De Salvo, Cosimo Gerardi, Rob van Schaijk, Salvatore A. Lombardo, Domenico Corso, Cristina Plantamura, Stella Serafino, Giuseppe Ammendola, Michiel van Duuren, Pierre Goarin, Wan Yuet Mei, Kees van der Jeugd, Thierry Baron, Marc Gély, Pierre Mur, and Simon Deleonibus, “Performance and Reliability Features of Advanced Nonvolatile Memories Based on Discrete Traps (Silicon Nanocrystals, SONOS)”, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 4, NO. 3, SEPTEMBER 2004 [1-22] www.intel.com/technology/architecture-silicon/22nm/ [1-23] N. Singh, K. D. Buddharaju, S. K. Manhas, A. Agarwal, S. C. Rustagi, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, “Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications”, IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 3107-3118, Nov 2008. [1-24] C. Hu, “Modern Semiconductor Devices for Integrated Circuit”, (Prentice Hall, New Jersey, 2008), pp. 299-300. [1-25] M. Bohr, “The Evolution of Scaling from the Homogeneous Era to the Heterogeneous Era”, IEDM Tech. Dig., 2011, pp. 1-6. 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Chapter 2
[2-1] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells-an overview”, Proceedings of IEEE, Vol. 85, pp. 1248, 1997. [2-2] Tseung-Yuen Tseng, Simon Min Sze, “NONVOLATILE MEMORIES”, AMERICAN SCIENTIFIC PUBLISHERS, p38-39 [2-3] M. Lenzlinger and E. H. Snow, J. Appl. Phys. 40, 278, 1969. [2-4] Z. T. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, IEEE Trans. Electron. Dev. 49, 1606, 2002. [2-5] M. H. White, Y. Yang, A Purwar, and M. L. French, IEEE Trans. Compon., Packag., Manuf Techno!. A 20, 190, 1997. [2-6] M. She, “Semiconductor Flash Memory Scaling”, Ph.D. Thesis, University of California at Berkeley, 2003. [2-7] Simon Tam, Ko, P.-K, Chenming Hu, “Lucky-Electron Model of Channel Hot-Electron Injection in MOSFET’s”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-31, NO. 9, SEPTEMBER 1984 [2-8] T. Ohnakado , K. Mitsunaga , M. Nunoshita , H. Onoda , K. Sakakibara , N. Tsuji , N. Ajika , M. Hatanaka , and H. Miyoshi , “Novel Electron Injection Method Using Band - to – Band Tunneling Induced Hot Electron (BBHE) for Flash Memory with a p - Channel Cell”, IEDM Tech. Dig ., pp. 279 – 282 , 1995 . [2-9] T.Y.Chan, J.Chen, P.K.Ko and C.Hu, “The Impact of Gate-Induced Drain Leakage Current on MOSFET Scaling,” IEDM Tech. Dig., 1987, p.718 [2-10] C.Chang and J.Lien, “CORNER-FIELD INDUCED DRAIN LEAKAGE IN THIN OXIDE MOSFETS”, IEDM Tech. Dig., 1987, p.714 [2-11] Takahiro Ohnakado, Hiroshi Onoda, Osamu Sakamoto, Kiyoshi Hayashi, Naho Nishioka, Hiroshi Takada, Kazuyuki Sugahara, Natsuo Ajika, and Shin-ichi Satoh, “Device characteristics of 0.35 μm P-channel DINOR flash memory using band-to-band tunneling-induced hot electron (BBHE) programming”, IEEE TED, VOL. 46, NO. 9, SEPTEMBER 1999
Chapter 3
[3-1] Sentaurus TCAD, 2011 Synopsys.
Chapter 4
[4-1] Jaehoon Jang, Han-Soo Kim, Wonseok Cho, Hoosung Cho, Jinho Kim, Sun Il Shim, Younggoan Jang, Jae-Hun Jeong, Byoung-Keun Son, Dong Woo Kim, Kihyun Kim, Jae-Joo Shim, Jin Soo Lim, Kyoung-Hoon Kim, Su Youn Yi, Ju-Young Lim, Dewill Chung, Hui-Chang Moon, Sungmin Hwang, Jong-Wook Lee, Yong-Hoon Son, U-In Chung, Won-Seong Lee, “Vertical Cell Array using TCAT(Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory”, VLSI dig., 2009, p.192. [4-2] Erh-Kun Lai, Hang-Ting Lue, Yi-Hsuan Hsiao, Jung-Yu Hsieh, Chi-Pin Lu, Szu-Yu Wang, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, +Jeng Gong, Kuang-Yeu Hsieh, Rich Liu, and Chih-Yuan Lu “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory”, IEDM tech. dig, 2006. [4-3] Hang-Ting Lue, Tzu-Hsuan Hsu, Yi-Hsuan Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, Szu-Yu Wang, Jung-Yu Hsieh, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, Kuang-Yeu Hsieh, and Chih-Yuan Lu, “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device” VLSI, 2010, p.131.
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