臺灣博碩士論文加值系統

在本篇論文中，我們提出了兩種應用於低功率事件驅動感知平台的全數位操控線性穩壓器。兩個全數位操控線性穩壓器皆實現在台積電65奈米低功耗CMOS製程，並可運作在近臨界操作電壓。
在第一個全數位操控線性穩壓器中，使用數位錯誤偵測器取代類比放大器。一種新的製程、電壓、溫度感知設計用來減輕環境變異，並提升全數位操控線性穩壓器的解析度。
在第二個全數位操控線性穩壓器中，使用以比較器為基礎的錯誤偵測器取代類比放大器。在不同的環境變異與負載變化下，我們提出兩種方法來調整PMOS的強度，以達到降低輸出漣漪的目的。

In this thesis, two digitally controlled linear voltage regulators are proposed for event-driven energy-efficiency sensing platform. Both digitally controlled linear voltage regulators are implemented on TSMC 65-nm low-power bulk CMOS technology and designed for near-/sub- threshold operations.
The first digitally controlled linear voltage regulator includes a digital error detector (DED), which is the replacement of the analog error amplifier. A novel Process-Voltage-Temperature (PVT) –aware design is implemented to mitigate environmental variations and to guarantee the resolution of linear voltage regulator.
In the second digitally controlled linear voltage regulator, a comparator-based error detector is proposed to replace analog error amplifier. Two methods are introduced to reduce self-generated output ripple by adjusting the PMOS strength for PVT and load variations.

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Research Goal and Major Contributions 2
1.3 Organization 4
Chapter 2 Overview of DC-DC Converter 6
2.1 Introduction 6
2.2 Categories of DC-DC Converters 7
2.2.1 Switched Capacitor 8
2.2.2 Switching Regulator 9
2.2.3 Linear Voltage Regulator 14
2.2.4 Comparison of DC-DC Converters 17
2.2.5 Benefit of Integrated Voltage Regulator 18
2.2.6 DC-DC Converters with Hybrid Operation 19
2.3 Digitally Controlled Low-dropout Voltage Regulator 21
2.4 The Terms and the Definitions of Low-dropout Voltage Regulator 23
2.4.1 Dropout Voltage 23
2.4.2 Quiescent Current 24
2.4.3 Standby Current 26
2.4.4 Power Efficiency 26
2.4.5 Transient Response 26
2.4.6 Line Regulation 27
2.4.6 Load Regulation 28
2.4.7 Power Supply Rejection 28
2.5 Summary 29
Chapter 3 PVT-Aware Digitally Controlled Linear Voltage Regulator 31
3.1 System Architecture of Proposed Digitally Controlled Linear Voltage Regulator 32
3.1.1 Function Work of PVT-aware Digital Error Detector 33
3.1.2 Control Logic and Push/Pull Devices 34
3.2 Digital Error Detector without PVT Compensation 35
3.2.1 Simulation Results of Digital Error Detector without PVT Compensation 36
3.3 PVT-Aware Digital Error Detector 38
3.3.1 PVT Sensor 38
3.3.2 Phase Detector 40
3.3.3 Compensation Circuits 41
3.3.4 Simulation Results of PVT-Aware DED 43
3.4 Experimental Results of Proposed PVT-Aware Digitally Controlled Linear Voltage Regulator 45
3.5 Summary 51
Chapter 4 All Digitally Controlled Linear Voltage Regulator with PMOS Strength Self-Calibration 52
4.1 System Architecture of Proposed Digitally Controlled Linear Voltage Regulator 53
4.2 Comparator-Based Error Detector and Voltage Divider 54
4.3 Mechanism of Control Logic and Grouped Push Devices 57
4.4 Mechanism of PMOS Strength Calibration 60
4.4.1 Analysis of Current Driving Capability of Active Power PMOSs Corresponding to Q[1:6] for PVT Variations 61
4.4.2 Circuit Used to Adjust Ripple Reduction Signal Q[1:6] 63
4.4.3 First Method (Coarse-Tune Ripple Reduction) 64
4.4.4 Second Method (Fine-Tune Ripple Reduction) 66
4.4.5 Summary of Mechanism of Ripple Reduction 71
4.5 Summary 72
Chapter 5 Design Implementation and Analysis of 0.6V Input Voltage All Digitally Controlled Linear Voltage Regulator 73
5.1 Performance of Proposed Digitally Controlled Linear Voltage Regulator 74
5.1.1 Start-up Transient Response 74
5.1.2 Load Transient Response 75
5.1.3 Response Time for Dynamic Voltage Scaling 76
5.1.4 Quiescent Current and Current Efficiency 79
5.2 Performance Comparison with Precious Works 81
5.2.1 Previous Works of Low Input Voltage Digitally Controlled Linear Voltage Regulators 81
5.2.2 Performance Comparison 83
5.3 Summary 84
Chapter 6 Conclusions and Future Work 85
6.1 Conclusions 85
6.2 Future Work 85
Reference 87

Chapter 1
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Samsung Tips $100 million IOT Strategy, EE Times 11/11/2013
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Chapter 2
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Chapter 3
[3.1] Y. Okuma, K. Ishida, Y. Ryu, X. Zhang, P.-H. Chen, K. Watanabe, M. Takamiya, and T. Sakurai, “0.5-V input digital LDO with 98.7% current efficiency and 2.7-μA quiescent current in 65nm CMOS,” IEEE Custom Integrated Circuits Conf. (CICC), pp. 1–4, Sep. 2010.
[3.2] Y. Kim, and P. Li, "A 0.38V near/sub- VT digitally controlled low-dropout regulator with enhanced power supply noise rejection in 90nm CMOS process," IET Circuit, Devices & Systems, vol. 7, no. 1, pp.31 - 41, Jan 2013
[3.3] K. Otsuga, M. Onouchi, Y. Igarashi, T. Ikeya, S. Morita, K. Ishibashi, and K. Yanagisawa, "An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor," IEEE International SOC Conference (SOCC), pp.11-14, Sept. 2012
[3.4] J.-H. Wang, C.-H. Tsai, and S.-W Lai, "A Low-Dropout Regulator With Tail Current Control for DPWM Clock Correction," IEEE Transactions on Circuits and Systems II: Express Briefs, vol.59, no.1, pp.45-49, Jan. 2012
[3.5] W.-C. Hsieh, and W. Hwang, "All Digital Linear Voltage Regulator for Super- to Near-Threshold Operation," IEEE Trans. VLSI Syst., vol.20, no.6, pp.989-1001, June 2012
[3.6] P.-C. Wu, Y.-P. Kuo, C.-S. Wu, C.-T. Chuang and W. Hwang, "PVT – Aware Digitally Controlled Voltage Regulator Design for Ultra-Low-Power (ULP) DVFS Systems," IEEE International SOC Conference (SOCC), Sept. 2014

Chapter 4
[4.1] J.F. Bulzacchelli, Z. Toprak-Deniz, T.M. Rasmus, J.A. Iadanza, W.L. Bucossi, Kim Seongwon, R. Blanco, C.E. Cox, M. Chhabra, C.D. LeBlanc, C.L. Trudeau, and D.J. Friedman, "Dual-Loop System of Distributed Microregulators With High DC Accuracy Load Response Time Below 500ps, and 85-mV Dropout Voltage," IEEE J. Solid-State Circuits, vol.47, no.4, pp.863-874, April. 2012
[4.2] Z. Toprak-Deniz, J.F. Bulzacchelli, T.M. Rasmus, J.A. Iadanza, W.L. Bucossi, Kim Seongwon, R. Blanco, C.E. Cox, M. Chhabra, C.D. LeBlanc, C.L. Trudeau, and D.J. Friedman, " Dual-Loop System of Distributed Microregulators With High DC Accuracy Load Response Time Below 500ps, and 85-mV Dropout Voltage," Symposium on VLSI Circuits, pp.274-275, June. 2011
[4.3] Z. Toprak-Deniz, M. Sperling, J.F. Bulzacchelli, G. Still, R. Kruse, Kim Seongwon, D. Boerstler, T. Gloekler, R. Robertazzi, K. Stawiasz, and T. Diemoz, " Distributed system of digitally controlled microregulators enabling pre-core DVFS for the POWER8TM microprocessor," International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp.98-99, Feb. 2014

Chapter 5
[5.1] Y. Okuma, K. Ishida, Y. Ryu, X. Zhang, P.-H. Chen, K. Watanabe, M. Takamiya, and T. Sakurai, “0.5-V input digital LDO with 98.7% current efficiency and 2.7-μA quiescent current in 65nm CMOS,” IEEE Custom Integrated Circuits Conf. (CICC), pp. 1–4, Sep. 2010.
[5.2] Y. Kim, and P. Li, "A 0.38V near/sub- VT digitally controlled low-dropout regulator with enhanced power supply noise rejection in 90nm CMOS process," IET Circuit, Devices & Systems, vol. 7, no. 1, pp.31 - 41, Jan 2013
[5.3] W.-C. Hsieh, and W. Hwang, "All Digital Linear Voltage Regulator for Super- to Near-Threshold Operation," IEEE Trans. VLSI Syst., vol.20, no.6, pp.989-1001, June 2012
[5.4] P.-C. Wu, Y.-P. Kuo, C.-S. Wu, C.-T. Chuang and W. Hwang, "PVT – Aware Digitally Controlled Voltage Regulator Design for Ultra-Low-Power (ULP) DVFS Systems," IEEE International SOC Conference (SOCC), Sept. 2014
[5.5] J.F. Bulzacchelli, Z. Toprak-Deniz, T.M. Rasmus, J.A. Iadanza, W.L. Bucossi, Kim Seongwon, R. Blanco, C.E. Cox, M. Chhabra, C.D. LeBlanc, C.L. Trudeau, and D.J. Friedman, "Dual-Loop System of Distributed Microregulators With High DC Accuracy Load Response Time Below 500ps, and 85-mV Dropout Voltage," IEEE J. Solid-State Circuits, vol.47, no.4, pp.863-874, April. 2012