臺灣博碩士論文加值系統

在本篇論文中，兩個具高電壓變異容忍度與高延遲解析度之全數位晶片內延遲量測電路設計應用於高效能的系統晶片中被提出，其中一個電路為所提出的晶片內延遲量測電路，另一個則為所提出的寬範圍晶片內延遲量測電路。所提出的兩個晶片內延遲量測電路不僅不需要任何額外的自我偏壓或校正電路即可對電壓變異擁有高抵抗能力而且亦具有高的延遲量測解析度。
所提出的晶片內延遲量測電路被實現在TSMC 90nm標準CMOS 製程中，從模擬結果顯示其延遲量測解析度可以被改善至 1.04ps，並且隨著 + 10% 的供應電壓變異其平均延遲解析度為 11fs。所提出的寬範圍晶片內延遲量測電路被實現在TSMC 0.18μm標準CMOS 製程中，從模擬結果顯示其延遲量測解析度可以被改善至大約 1ps，並且隨著 + 10% 的供應電壓變異其平均延遲變異量為 0.923%。本篇所提出的兩個晶片內延遲量測電路皆能使用全數位設計的方式來實現，因此它們皆非常適合於系統晶片的應用以及易整合於系統中。

In this thesis, two high delay resolution and high supply voltage variation tolerance all-digital on-chip delay measurement (OCDM) circuits for the high performance system-on-chip (SoC) applications are proposed. One is proposed OCDM circuit and the other is proposed wide-range OCDM circuit. Both of proposed OCDM circuits not only have a high immunity to supply voltage variations without extra self-biasing or calibration circuit, but also achieve high delay measurement resolution.
The proposed OCDM circuit is implemented in TSMC 90nm standard CMOS technology, and simulation results show that delay measurement resolution can be improved to 1.04ps, and the average delay resolution is 11fs with + 10% supply voltage variation. The proposed wide-range OCDM circuit is implemented in TSMC 0.18μm CMOS technology, and simulation results show that delay measurement resolution can be improved to about 1ps, and the average delay variation is 0.692% with + 10% supply voltage variation.
The proposed OCDM circuits can be implemented in all-digital design manner, making it very suitable for SOC application as well as system-level integration.

Abstract (In Chinese)……………………………………………………………………. i
Abstract………………………………………………………………………………….ii
Acknowledgement (In Chinese)………………………………………………………..iii
Content………………………………………………………………………………….iv
List of Table……………………………………………………………………………..v
List of Figure…………………………………………………………………………...vi
Chapter 1 Introduction…………………………………………………………………1
1.1 Motivation………………………………………………………..………...…1
1.2 OCDM Architecture Overview …………………………………….………...6
1.3 Thesis Organization…………………………………………………………...9
Chapter 2 Vernier Delay Line with Low Supply Sensitivity Design…...........………11
2.1 Vernier Delay Line Architecture Overview.....…………………………...11
2.2 Proposed Vernier Delay Line with Low Supply Sensitivity Ⅰ...……..……13
2.3 Proposed Vernier Delay Line with Low Supply Sensitivity Ⅱ...…………..18
2.4 Summary ………...………………...………………………………………..22
Chapter 3 On-Chip Delay Measurement Design ………….…………………………23
3.1 Proposed OCDM Architecture Overview …………………….…….………23
3.2 Proposed Wide-Range OCDM Architecture Overview ……………………27
3.3 Circuit Design……………………………………………………………….34
3.3.1 Phase Detector……………………….……….….............................34
3.3.2 Interpolator….…………………………………….……………...38
3.4 OCDM Design Flow………………………………………….……………..44
3.5 Summary……………………………………………………………….……46
Chapter 4 Experimental Results………………………..…………………………….47
4.1 Proposed OCDM Architecture Experimental Results ……...........................47
4.1.1 Simulation Results…………………………………………………...47
4.2 Proposed Wide-Range OCDM Architecture Experimental Results………...48
4.2.1 Simulation Results…………………………………………………...48
4.2.2 Measurement Methodology………………………………………….51
4.3 Summary………………………………………………………………..…...55
Chapter 5 Conclusions and Future Work…………………..………………………...56
Reference……………………………………………………………………………….58

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