臺灣博碩士論文加值系統

論文中設計0.18-μm CMOS低電壓高平衡壓控振盪器、無直流功率損耗混頻器、與具AM-to-PM雜訊抑制之頻率合成器，其可應用於LTE與WiMAX。低電壓高平衡壓控振盪器共設計了三顆晶片。第一顆晶片為高平衡四相位壓控振盪器，其利用基極端交互耦合產生四相位訊號，並且採用動態轉導匹配技術來改善輸出差動波形的振幅不平衡。量測結果，相位誤差小於 ，振幅誤差小於6.9 %，電壓源為1 V下功率消耗為4.4 mW，在可調頻寬3193 – 3605 MHz的範圍內，距載波中心頻率1-MHz的相位雜訊為-130.6 – -133.7 dBc/Hz。第二顆晶片使用基體偏壓技術降低電晶體臨界電壓，使用電流源動態轉導匹配技術改善振幅不平衡，且於PMOS電流源汲極端設計雜訊濾波器，抑制電流源之雜訊溫度。量測結果，電壓源為0.7 V下功率消耗為3 mW，在可調頻寬3387 – 3696 MHz的範圍內，距載波中心頻率1-MHz的相位雜訊為小於-121 dBc/Hz，相位誤差小於 ，振幅誤差小於2.8 %。第三顆晶片設計概念與第二顆相似，差別在於使用射頻等效阻抗匹配技術，在無直流跨壓下，達到改善輸出波形不平衡的目的。量測結果，電壓源為0.45 V下功率消耗為0.76 mW，在可調頻寬3367 – 3919 MHz的範圍內，距載波中心頻率1-MHz的相位雜訊小於-122 dBc/Hz，相位誤差小於 ，振幅誤差小於2.9 %。
無直流功率損耗混頻器晶片利用本地振盪訊號功率驅動電晶體，並使用電容使直流準位提升至零，實現無直流功率損耗且具轉換增益之混頻器。量測結果顯示，射頻端2.0 – 4.0 GHz混頻至固定中頻端10 MHz，功率消耗為0 mW，雜訊指數為20.7 – 24.5 dB，電壓轉換增益為-0.21 – 4.60 dB，輸入端 為-15.6 – -12.5 dBm。
具AM-to-PM雜訊抑制之頻率合成器晶片使用非線性PFD與電荷幫浦降低鎖定時間，並且利用差異積分器與降低AM-to-PM雜訊轉換之壓控振盪器以達到抑制突波與改善相位雜訊的效果。壓控振盪器量測結果顯示，電壓源為1.8 V下，功率消耗為5.76 mW，在可調頻寬1603 –2071 MHz的範圍內，距載波中心頻率1-MHz的相位雜訊為-128.1 dBc/Hz。頻率合成器量測結果顯示，電壓源為1.73 V下，功率消耗為20.1 mW，距載波中心頻率1-MHz的相位雜訊為-99.0 dBc/Hz，鎖定時間約為30 ms。

In this thesis, three types of CMOS MMICs in 0.18-?m CMOS technology were designed for LTE and WiMAX applications, which include low-voltage high-balance voltage controlled oscillators (VCO), self-biased mixer, and phase-locked loop with AM-to-PM noise suppression. In the first type of CMOS VCOs, there are three taped-out chips designed at 3.5 GHz, which are a 1-V quadrature voltage-control oscillator (QVCO), and 0.7-V/0.45-V differential VCOs. The QVCO was designed with an dynamic transconductance matching technique for eliminating the output amplitude imbalance. The measurement result shows that the phase error is < 0.8°and the amplitude error is < 6.9 %. The phase noise is from -130.6 to -133.7 dBc/Hz at 1-MHz offset frequency from the carrier over the 3193 to 3605 MHz tuning band. The power consumption is 4.4 mW from a 1 V supply. The 0.7 V and 0.45 V differential VCOs were designed for low-voltage operation by using the body bias to reduce threshold voltage, the dynamic transconductance matching for amplitude balance, and a drain noise filter for the thermal noise suppression of the current-source. The measurement result shows that the operating voltage can be as low as 0.7 V and 0.45 V. The power consumption is 0.76 mW from a 0.45 V supply, where the phase noise is less than -122 dBc/Hz at 1-MHz offset from the carrier of 3367-3919 MHz and the phase error is 2.3°and the amplitude error is 2.9 %. The power consumption is 3 mW from a 0.7 V supply, where the phase noise is less than -121 dBc/Hz at 1-MHz offset from the carrier of 3387-3696 MHz and the phase error is 0.3° and the amplitude error is 2.8 %.
The self-biased active mixer utilizes the LO-induced dc voltage to dynamically bias the MOSFET such that conversion gain can be obtained without needing external dc power supply. The measurement shows that the designed mixer MMIC has a measured voltage gain of 4.6 dB with zero dc power consumption. The input is -12.5 dBm and the noise figure is 20.7-24.5 dB for the RF band of 2.0 to 4.0 GHz and 10 MHz IF frequency.
The implemented frequency synthesizer includes a non-linear phase frequency detector (PFD), charge pump (CP), sigma-delta modulator, and the voltage-control oscillator with AM-to-PM noise suppression. The measured phase noise is -99.0 dBc/Hz at 1 MHz offset and the settling time is 30 ms. the power consumption is 20.1 mW from a 1.7 V supply.

目錄 ……………………………………………………………………………….i
圖目錄 ……………………………………………………………………………...iii
表目錄 ……………………………………………………………………………...vi
第一章 緒論 1
1.1 研究背景與動機 1
1.2 IEEE 802.16(WiMAX) / LTE系統簡介 2
1.3 文獻探討 3
1.3.1 CMOS四相位壓控振盪器 3
1.3.2 高平衡輸出電路架構 7
1.4 研究目的與論文架構 11
第二章 運用動態轉導匹配技術之高平衡輸出四相位壓控振盪器 12
2.1 電路分析 12
2.2 模擬與量測結果 18
第三章 低於1 V之CMOS差動壓控振盪器 23
3.1 0.7 V差動壓控振盪器 23
3.1.1 電路分析 23
3.1.2 模擬與量測結果 27
3.2 0.45V差動壓控振盪器 32
3.2.1 電路分析 32
3.2.2 模擬與量測結果 34
第四章 CMOS無功率損耗混頻器設計 39
4.1 混頻器介紹 39
4.1.1 轉換增益 40
4.1.2 雜訊指數 42
4.1.3 線性度 44
4.1.4 隔離度與直流偏移 46
4.2 電路分析 47
4.3 模擬與量測結果 52
第五章 具AM-to-PM雜訊抑制功能之分數型頻率合成器 59
5.1 分數型頻率合成器架構簡介 59
5.2 多模數除頻器設計 60
5.3 差異積分調變器設計 62
5.4 無dead zone非線性相位頻率偵測器設計 69
5.5 電荷幫浦設計 76
5.6 低雜訊之壓控振盪器設計 78
5.7 低通濾波器設計 81
5.8 頻率合成器量測結果 82
第六章 結論 86
參考文獻 88

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