臺灣博碩士論文加值系統

近年來矽半導體製程、電腦輔助設計軟體、以及電路設計技巧的進步，已讓數位與類比電路的整合度大大提高，反觀射頻電路預做整合的話，仍有許多困難要克服，目前有許多無法整合的高頻電路中，如射頻濾波器、功率放大器以及射頻開關等電路。其中射頻開關不能與系統整合的原因，主要是以插入損耗(insertion loss)過高以及功率承載(power handling)能力低，這些問題的產生主要是矽基板具導電性，造成訊號會從基板流失。本論文預使用TSMC 0.18μm 1P6M CMOS製程結合微機電後製程的使用將射頻開關整合入矽晶片。製作高Q電感，作阻抗匹配，降低插入損耗。其中利用微機電製程蝕刻電路中電感元件、傳輸線下方的矽基板使其懸空，減少電路的插入損耗，並利用ADS(Advanced Design System)_Momentum 模擬所設計的電路，可得知使用微機電製程蝕刻矽基板可以減少23.7%的插入損耗。而開關TX端經ADS模擬後功率承載(Pin-1dB)=27.390dBm、插入損耗(insertion loss)=0.538dB。

In past years, silicon-base semiconductor process, computer-aided design tools, and circuit design skills have all made great progress, and it makes the high integration between digital and analog circuits. However, it is difficult to integrate with radio frequency (RF) circuits, such as RF filter, RF power amplifier, and RF switch. Among those RF circuits, the reasons of that RF switch could not be integrated in system are high insertion loss and low power handling. Those issues occur because the silicon substrate is conductance material inducing power loss. This work
use TSMC 0.18μm 1P6M CMOS process and Micro-electro-mechanical Systems (MEMS) post-process to integrate with RF switch on a silicon chip. MEMS post-process is used to etch bulk of the inductance device and transmission line to reduce insertion loss of the switch circuit. Using ADS(Advanced Design System)_Momentum to simulate switch circuit and the insertion loss would be reduced 23.7%. The TX node of the switch circuit use ADS_Momentum to simulate power handling P1dB=27.390dBm, insertion loss=0.538dB.

目錄
第一章 緒論1
第二章 開關電路原理說明6
2.1 開關電路功能概述6
2.2 開關設計原理與分類7
第三章 微機電技術介紹11
3.1 微機電作用說明11
3.2 微機電技術起源12
3.3 微機電技術介紹12
3.4 微機電技術於矽製程應用14
第四章 開關電路設計16
4.1 2.4G CMOS射頻開關電路之設計16
4.1.1 電路設計目標16
4.1.2 電路架構設計17
4.2 微機電製程於電路中之應用22
4.3 2.4G CMOS射頻開關電路製作與模擬26
4.3.1 電路特性模擬27
4.3.2 變換製程參數模擬36
4.3.3 晶片量測46
第五章 結論47
參考文獻50

圖 目 錄
圖1.1 通訊系統架構示意圖1
圖2.1.1 通訊系統架構概要圖7
圖2.2.1 開關電路基本分類圖7
圖2.2.2 FET開關電路示意圖9
圖2.2.3 FET 開關電路TX側導通動作原理解析10
圖2.2.4 FET 開關電路RX側導通動作原理解析10
圖3.4.1 矽基板蝕刻類別示意圖15
圖4.1.1 電路設計流程圖17
圖4.1.2 典型CMOS開關電路架構18
圖4.1.3 開關電路設計架構圖20
圖4.1.4 MOS FET 寄生電容示意圖21
圖4.1.5 電感模擬與示意圖21
圖4.2.1(a)(b)(c)CMOS製程進行矽基板蝕刻流程圖23
圖4.2.2 開關未使用MEMS後製程蝕刻插入損耗、功率承載模擬結果圖25
圖4.2.3 開關使用MEMS後製程蝕刻插入損耗、功率承載模擬結果圖25
圖4.3.1 開關電路設計布局圖26
圖4.3.2 開關TX端功率承載模擬結果圖27
圖4.3.3 開關TX端插入損耗模擬結果圖28
圖4.3.4 開關TX端反射損耗模擬結果圖29
圖4.3.5 開關TX端隔離度模擬結果圖30
圖4.3.6 開關RX端功率承載模擬結果圖31
圖4.3.7 開關RX端插入損耗模擬結果圖32
圖4.3.8 開關RX端反射損耗模擬結果圖33
圖4.3.9 開關RX端隔離度模擬結果圖34
圖4.3.10 開關TX端製程參數T/T插入損耗模擬結果圖36
圖4.3.11 開關TX端製程參數F/F插入損耗模擬結果圖37
圖4.3.12 開關TX端製程參數S/S插入損耗模擬結果圖38
圖4.3.13 開關TX端製程參數F/S插入損耗模擬結果圖39
圖4.3.14 開關TX端製程參數S/F插入損耗模擬結果圖40
圖4.3.15 開關RX端製程參數T/T插入損耗模擬結果圖41
圖4.3.16 開關RX端製程參數F/F插入損耗模擬結果圖42
圖4.3.17 開關RX端製程參數S/S插入損耗模擬結果圖43
圖4.3.18 開關RX端製程參數F/S插入損耗模擬結果圖44
圖4.3.19 開關RX端製程參數S/F插入損耗模擬結果圖45
圖4.3.20 電路量測考量示意圖46

表 目 錄
表一 過去文獻特性比較4
表二 模擬結果整理表35
表三 模擬結果與文獻比較48

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