臺灣博碩士論文加值系統

我們利用實驗室成員所提出的平台式 (Platform-Based ) 系統單晶片(System-on-Chip, SOC) 設計流程以及矽智產(Silicon Intellectual Property, SIP) 設計和整合方法 (Integration methodology)，以軟硬體共同設計的方式完成一個JPEG2000編碼器。我們特別著重在硬體加速器部份和中央處理器 (CPU) 內軟體部份的同時執行 (concurrent execution) 規劃上。在我們採用的可程式化系統單晶片平台上，JPEG2000以離散小波轉換 (Discrete Wavelet Transform, DWT) 和區塊編碼 (Embedded Block Coding with Optimized Truncation, EBCOT) 硬體加速器等循序執行加速後，和 JPEG2000 以純軟體方式執行的時間相比較，約可減少 70% 的執行時間。而利用我們所提出的同時執行規劃，我們可以更進一步地縮短約 14% 的執行時間。在此，我們將在所提出的系統上，敘述我們的實作經驗。

We implement a JPEG2000 encoder based on an internally developed hardware/software codesign methodology. We emphasize on the concurrent execution of hardware accelerator IPs and software running on the CPU. In a programmable SOC platform, hardware acceleration of DWT and EBCOT Tier-1 sequentially gives us 70% reduction in total execution time. The proposed concurrent scheme achieves additional 14% saving. We describe our experience in bringing up such a system.

ABSTRACT
CONTENTS
LIST OF FIGURES
LIST OF TABLES
CHAPTER 1
INTRODUCTION
1.1 JPEG2000 STILL IMAGE CODING SYSTEM
1.1.1 Profiling Analysis
1.2 PLATFORM-BASED SOC METHODOLOGY
1.2.1 An Overview of AMBA-based platform architecture
1.2.2 SOC Design Flow
CHAPTER 2
PREVIOUS WORK
2.1 SPEEDUP WITH PARALLEL PROCESSING
2.2 SPEEDUP WITH CO-PROCESSORS
2.3 SPEEDUP WITH HARDWARE ACCELERATORS
2.4 SPEEDUP WITH HARDWIRED ASIC
2.5 MOTIVATION
CHAPTER 3
PROPOSED APPROACH
3.1 PURE SOFTWARE PERFORMANCE
3.2 SEQUENTIALLY-ACCELERATION OF DWT AND EBCOT TIER-1
3.3 CONCURRENT EXECUTION OF HARDWARE AND SOFTWARE
CHAPTER 4
EXPERIMENTAL RESULTS
4.1 EMBEDDED SOFTWARE MODIFICATION
4.2 HARDWARE ACCELERATOR INTEGRATION
4.3 HARDWARE/SOFTWARE CO-SIMULATION
4.4 EXPERIMENTAL RESULTS
CHAPTER 5
CONCLUSION
BIBLIOGRAPHY

[1] AMBATM Specification (Rev 2.0), ARM Ltd., Available: http://www.arm.com/products/solutions/AMBA_Spec.html
[2] ARM Developer Suite 1.2 user guide, ARM Ltd., Available: http://www.arm.com/pdfs/DUI0064D_ADS1_2_GettingStarted.pdf
[3] A. Skodras, C. Christopoulos, and T. Ebrahimi, “The JPEG 2000 Still Image Compression Standard,” IEEE Signal Processing Magazine, vol. 18, pp. 36-58, Sept 2001
[4] C. B. Fan, “An IP Integration Methodology for AMBA-based SOC,” Master thesis, University of National Tsing Hua University, Hsinchu, Taiwan, June 2004
[5] C. C. Chang, “A Parameterized On-Chip-Bus-Compliant FDWT/IDWT Accelerator IP Generator,” Master thesis, University of National Tsing Hua University, Hsinchu, Taiwan, June 2004
[6] H. C. Fang, C. T. Huang, Y. W. Chang, T. C. Wang, P. C. Tseng, C. J. Lian, and L. G. Chen, “81MS/s JPEG 2000 single-chip encoder with rate-distortion optimization,” in Proceedings of 2004 IEEE International Solid-State Circuits Conference (ISSCC 2004), pp.328-329, February, 2004.
[7] H. Tsutsui, T. Masuzaki, T. Izumi, T. Onoye, and Y. Nakamura, “High Speed JPEG2000 Encoder by Configurable Processor,” in the 2002 Asia-Pacific Conference on Circuits and Systems, pp. 45-50, October 2002
[8] Information technology-Digital compression and coding of continuous-tone still images: Requirements and guidelines, ISO/IEC, ISO/IEC 10918-1:1994, 1994.
[9] Jasper, Open source code for JPEG2000 standard part-1, Available: http://www.ece.uvic.ca/~mdadams/jasper/
[10] JJ2000, An implementation of the JPEG2000 standard in JAVA, Available: http://jj2000.epfl.ch
[11] JPEG-2000 Part 1 Final Draft International Standard(ISO/IEC FDIS15444-1),ISO/IEC JTC1/SC29/WG1 N1855, Aug. 2000
[12] K. Y. Jan, “A Platform-Based SOC Design Methodology and Its Application on JPEG Decoding,” Master thesis, University of National Tsing Hua University, Hsinchu, Taiwan, June 2004
[13] Literature: Embedded Software Design, ALTERA Corporation, Available: http://www.altera.com/literature/quartus2/lit-emb.jsp
[14] Literature: Excalibur, ALTERA Corporation, Available: http://www.altera.com/literature/lit-exc.jsp
[15] Literature: Quartus II Development Software, ALTERA Corporation, Available: http://www.altera.com/literature/lit-qts.jsp
[16] Literature: SOPC Builder, ALTERA Corporation, Available: http://www.altera.com/literature/lit-sop.jsp
[17] Literature: Xtensa Application Specific Microprocessor Solutions – Overview Handbook, Tensilica Inc., 2000
[18] M. Boden, J. Schneider, K. Feske, and S. Rulke, “Enhanced Reusability for SoC-based HW/SW Co-design,” in Proceeding of Euromicro Symposium on Digital System Design 2002, pp. 94-99, September 2002.
[19] M. D. Adams, “The JPEG-2000 Still Image Compression Standard,” A tutorial paper on JPEG 2000 distributed with the JasPer software , Available: http://www.ece.uvic.ca/~mdadams/papers/jpeg2000.pdf
[20] M. Martina, G. Masera, G. Piccinini, F. Vacca, and M. Zamboni, “Reconfigurable Coprocessor Based JPEG 2000 Implementation, “ in the 8th IEEE International Conference on Electronics, Circuits and Systems 2001, vol. 3, pp. 1227-1230, September 2001
[21] ModelSim SE users manual, Mentor Graphics Inc., Available: http://model.com/support/docs.asp?id=121
[22] M. Rabbani and D. Santa Cruz, “The JPEG2000 Still-Image Compression Standard,” short course at the 2001 International Conference in Image Processing (ICIP), Thessaloniki, Greece, October 11, 2001, Available: http://ltswww.epfl.ch/~dsanta/teaching/ICIP2001_JPEG2K.pdf
[23] OpenMP, Open specifications for Multi Processing, Available: http://www.openmp.org
[24] P. Coussy, A. Baganne, and E. Martin, “Platform-Based Design for Digital Signal Proceeding Systems: A Case Study of MPEG-2/JPEG2000 Encoder,” in IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions, vol. 2, pp.1361-1366, June 2002
[25] P. Meerwald, R. Norcen, and A. Uhl, “Parallel JPEG2000 Image Coding on Multiprocessors,” in the Proceedings International Parallel and Distributed Processing Symposium 2002, pp. 2-7, April 2002
[26] Product Page: JPEG2000 Video Codec, ADV-JP2000, Analog Devices, http://www.analog.com
[27] Product Page: JPEG2000 Codec, CS6590, Amphion Semiconductor Ltd., Available: http://www.amphion.com/cs6590.html
[28] S. Ramamurthy, S. Madhavankutty, V. Meena, and R. Gupta, “JPEG-2000 on An Advanced Architecture, Multiple Execution Unit DSP,” in IEEE International Symposium on Circuits and Systems 2002, vol. 4, pp. 325-328, May 2002
[29] StarCoreTM, Licensable DSP Technology, http://syatcore-dsp.com
[30] T. W. Hsieh, “Low Power and High Performance AHB-compliant EBCOT Architecture for JPEG2000 Encoding,” Master thesis, University of National Tsing Hua University, Hsinchu, Taiwan, June 2004
[31] Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Izumi, T. Onoye, and Y. Nakamura, “Design Framework For JPEG2000 Encoding System Architecture, “ in Proceeding of the 2003 International Symposium on Circuits and Systems, vol. 2, pp. 740-743, May 2003