臺灣博碩士論文加值系統

系統晶片內提供熱管理(thermal management)資訊之傳統全數位式溫度感測器，一則因為其使用最小尺寸溫度感測單元，再加上其使用省面積之簡易之單點校正去除製程變異演算器，故能達到面積小、功耗小、及取樣率高等優點。然而本研究分析結果指出，當使用和高階處理器一樣的前瞻奈米CMOS製程(如28奈米製程)來設計時，傳統全數位溫度感測器將面臨(1)極大的溫度感測誤差與(2)有限的溫度感測範圍等兩大嚴峻考驗。
為了克服上述問題，本研究利用(1)包含溫度感測係數、短通道長度效應、短通道寬度效應、臨界電壓變異等與電晶體特性相關之尺寸調整方法，及(2)具適應性補償係數調整之新型單點校正方法，透過晶片實作與實測結果證實，讓全數位溫度感測器縱然在28奈米製程下進行設計時，可以達到在0~100°C之感測範圍僅有4.7°C之感測誤差，足可與最先進之32 nm製程下類比式溫度感測器於-10~ 110°C之感測範圍達到之4.5°C之感測誤差性能匹敵，而仍保有面積更小、功耗更小、及取樣率高等優點。上述新型設計技術可以實現在本團隊先前所研發之全數位式架構上，而只需要適應性的調整補償係數即可。
也由於上述優點，本研究近一步顯示，此全數位式溫度感測器極為適合需要多顆溫度感測器之應用設計。當系統配備具有小型運算能力之運算單元時，所有溫度感測器上之校正運算都可移至該運算單元，進一步節省溫度感測器之面積，同時達到高速萃取溫度及溫度變化的目的，以完成有效的多點熱管理策略。本系統也經模擬證實，正透過實際下線進行晶片驗證中。

The increase in device density and speed of modern high performance processors cause chips to heat up and not removed quickly during runtime, thus resulting in thermal problems. The thermal management techniques are essential to be incorporated into systems to protect from damage. On-chip all-digital temperature sensors (TSs) have features as low cost, low power and easy integration. We design the all-digital TSs in 28-nm and integrate them in the variation monitoring and management system, which monitors the variations. However, the issues of the nominal voltage being near the zero-temperature- coefficient (ZTC) point, and the influence of serious process variations, cause the severe sensing errors. We design a new delay cell with improved temperature sensitivity. And a new method, adaptive one-point calibration, has better accuracy (4.7℃) than that of the conventional one-point calibration (7.6℃) with the similar calibration cost.

致謝辭 ii
中 文 摘 要 iii
Abstract - iv
目錄 1
第一章 緒論 9
1.1 研究背景 9
1.2 研究動機 11
1.3 論文架構 12
第二章 技術現況分析 13
2.1 指標性數位式溫度感測器的架構 16
2.1.1 雙延遲鎖相迴路溫度感測器(Dual delay-locked-loop TS) 16
2.1.2 頻率-數位轉換架構溫度感測器(Frequency-to-Digital Converter Based TS) 22
2.2 指標性內建式溫度感測器校正方法差異性分析 23
2.2.1 二點校準方法 (Two-point calibration) 23
2.2.2 單點方法 (One-point calibration) 24
2.2.3 自動校準方法 (Auto calibration) 24
2.3 內建式溫度感測器的擺放之分析 25
2.4 總結 25
第三章 基於既有全數位溫度感測器的架構並調整 27
3.1 溫度感測原理 28
3.2 感測器電路的架構 31
3.2.1 單延遲鎖相迴路(Single DLL-based)溫度感測器架構 31
第四章 28-nm溫度感測器之設計問題與解決方法 40
4.1 設計挑戰與分析 40
4.1.1 溫度感測係數之分析 41
4.1.2 製程變異對於感測精確度的影響 45
4.2 延遲單元(delay cell)的特性設計 45
4.2.1 使用Low-Vth (LVT)製程 46
4.2.2 短通道之通道長度與寬度對於Vth變異之影響 46
4.2.3 反相器架構設計 48
4.2.4 選用架構之尺寸再調整 49
第五章 應用於本研究感測器的校準方法之統整 51
5.1 除法標準化單點校準方法 (One-point calibration，1P) 51
5.1.1 校準原理 51
5.1.2 Single DLL-based TS的除法標準化單點校準操作流程 53
5.2 假自動校準方法 (Pseudo-auto calibration) 56
5.2.1 校準原理 56
5.2.2 Single DLL-based TS的除法標準化單點校準之操作流程 57
5.3 二點校準方法 (Two-point calibration，2P) 60
5.3.1 校準原理 60
5.3.2 實現於Single DLL-based TS的二點校準之操作流程 62
5.4 適應型單點校準方法 (Adaptive one-point calibration，Adap. 1P) 66
5.4.1 以趨勢推測求得第二點校準資訊 66
第六章 整合於變異偵測與管理系統之溫度感測器設計 69
6.1 變異偵測與管理系統之開發背景 69
6.2 系統整合之溫度感測器的電路改良與簡化 71
6.2.1 全客戶式電路的優化 71
6.2.2 感測器架構簡化 73
6.3 感測器的細部操作與控制流程 77
6.3.1 SPI資料協定 77
6.3.2 感測器操作時序 80
第七章 實驗結果 81
7.1 第一版測試晶片量測結果 81
7.1.1 量測感測誤差與校準方法之分析 86
7.1.2 調整取樣頻率之量測功率消耗 93
7.2 第二版整合於VMMS之感測器模擬結果 94
7.2.1 佈局後模擬感測誤差與校準方法之分析 98
第八章 總結與未來研究方向 103
8.1 總結 103
8.2 未來研究方向 104
參考文獻 105

[1]Alfred Yeung, Hamid Partovi, et al., “A 3GHz 64b ARM v8 Processor in 40nm Bulk CMOS Technology,” ISSCC Dig. Tech. Papers, pp. 110-112, Feb. 2014.
[2]Igarashi, M., Renesas Electron., et al., “A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores,” IEEE J. Solid-State Circuits, vol. 50, pp. 92-101, 2014.
[3]Nasser Kurd, Muntaquim Chowdhury, et al., “ Haswell: A Family of IA 22nm Processors,” ISSCC Dig. Tech. Papers, pp. 112-114, Feb. 2014.
[4]Fluhr, E.J., Baumgartner, S, et al., “The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking,” IEEE J. Solid-State Circuits, vol. 50, pp. 10-23, 2014.
[5]Rusu, S. ; Muljono, H., et al., “A 22 nm 15-Core Enterprise Xeon® Processor Family,” IEEE J. Solid-State Circuits, vol. 50, pp. 35-48, 2014.
[6]Andrew Danowitz, Kyle Kelley, et al., “CPU DB: Recording Microprocessor History,” Communications of the ACM, Vol. 55 No. 4, pp. 55-63, 2012.
[7]Pradip Bose, et al., “Exploring power management in multi-core systems,” Design Automation Conference (ASPDAC), 2012.
[8]C. Poirier, R. McGowen, C. Bostak, et al, “Power and Temperature Control on a 90nm Itanium®-Family Processor,” ISSCC Dig. Tech. Papers, pp. 304-305, Feb. 2005.
[9]Y.-W. Li, H. Lakdawala, “Smart Integrated Temperature Sensor - Mixed-Signal Circuits and Systems in 32-nm and Beyond,” IEEE Custom Integrated Circuits Conf., pp. 1-8, 2011.
[10]J. Shor, K. Luria and D. Zilberman, “Ratiometric BJT-Based Thermal Sensor in 32nm and 22nm Technologies,” ISSCC Dig. Tech. Papers, pp. 210-212, 2012.
[11]Herbert, S., Marculescu, D. , “Variation-aware dynamic voltage/frequency scaling,” IEEE High Performance Computer Architecture, pp. 301-312, 2009.
[12]T.-Y Kuo, et al, “An energy-efficient truly all-digital temperature sensor for SoC applications,” IEEE GLSVLSI, pp. 67-70, 2013.
[13]王進賢、郭子源，碩士論文，民國99年七月。臺灣嘉義縣：中正大學電機工程研究所。
[14]J. Clabes, J. Friedrich, M. Sweet, et al., “Design and implementation of the power5 microprocessor,” ISSCC Dig. Tech. Papers, pp. 56 – 57, Feb. 2004.
[15]M. Floyd, et al., “Introducing the Adaptive Energy Management Features of the Power7 Chip,” IEEE Micro, vol. 31, no. 2, pp. 60-75, 2011.
[16]S. Paek, W. Shin, J. Lee, et al., “All-Digital Hybrid Temperature Sensor Network for Dense Thermal Monitoring,” ISSCC Dig. Tech. Papers, pp. 260 - 261, 2013.
[17]P. Chen, C.-C. Chen, C.-C. Tsai, and W.-F. Lu, “A time-to-digital converter-based CMOS smart temperature sensor,” IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1642–1648, Aug. 2005.
[18]K. Woo, S. Meninger, T. Xanthopoulos, et al., “Dual-DLL-Based CMOS All-Digital Temperature Sensor for Microprocessor Thermal Monitoring,” ISSCC Dig. Tech. Papers, pp. 68-70, Feb. 2009.
[19]Dongwan Ha, Kyoungho Woo, Meninger, S, et al., “Time-Domain CMOS Temperature Sensors With Dual Delay-Locked Loops for Microprocessor Thermal Monitoring,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, pp. 1590 - 1601, 2011.
[20]Kisoo Kim, Hokyu Lee, et al., “A 366kS/s 400uW 0.0013mm2 Frequency- to-Digital Converter Based CMOS Temperature Sensor Utilizing Multiphase Clock,” IEEE Custom Intergrated Circuits Conference (CICC), pp.203-205, 2009.
[21]Sewook Hwang, Kisoo Kim, Hokyu Lee, et al., “A 0.008 mm2 500 uW 469 kS/s Frequency-to-Digital Converter Based CMOS Temperature Sensor With Process Variation Compensation,” IEEE Transactions on Circuits And Systems (TCASI), pp.1-8, 2013.
[22]T. Yang, S. Kim, P. R. Kinget and M. Seok, “0.6-to-1.0V 279μm2, 0.92μW temperature sensor with less than +3.2/-3.4°C error for on-chip dense thermal monitoring,” ISSCC Dig. Tech. Papers, pp. 282-283, Feb. 2014.
[23]Poki Chen, Chun-Chi Chen, Yu-Han Peng, Kai-Ming Wang, and Yu-Shin Wang, “A Time-Domain SAR Smart Temperature Sensor With Curvature Compensation and a 3σ Inaccuracy of -0.4℃~+0.6℃ Over a 0℃ to 90℃Range”, IEEE J. Solid-State Circuits, pp.600-609, 2010.
[24]Ching-Che Chung, Cheng-Ruei Yang, “An all-digital smart temperature sensor with auto-calibration in 65nm CMOS technology,” IEEE International Symposium on Circuits and Systems (ISCAS),pp. 4089–4092, 2010.
[25]C.-C. Chung and C.-R. Yang, “An autocalibrated all-digital temperature sensor for on-chip thermal monitoring,” IEEE Transactions on Circuits And Systems (TCASI), vol. 58, no2, pp.105-107, Feb. 2011.
[26]王進賢、詹凱霖，碩士論文，民國100年七月。臺灣嘉義縣：中正大學電機工程研究所。
[27]王進賢，「VLSI電路設計」。民國89年，初版，pp. 124-127。臺北市：高立。
[28]S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981.
[29]I. M. Filanovsky and Ahmed Allam, “Mutual Compensation of Mobility and Threshold Voltage Temperature Effects with Applications in CMOS Circuits,” IEEE Transactions on Circuits And Systems (TCASI), vol. 48, no. 7, July 2001.
[30]Cho, M., Khellah, M., Chae, K., Ahmed, K, et al, “Characterization of Inverse Temperature Dependence in logic circuits,” IEEE Custom Intergrated Circuits Conference (CICC), pp.1-4, Sept. 2012.
[31]M. A. P. Pertijs, K. A. A. Makinwa, and J. H. Huijsing, “A CMOS smart temperature sensor with a 3σ inaccuracy of ±0.1℃ from -55℃ to 125℃ ,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2805–2815,Dec. 2005.
[32]A. L. Aita, M. A. P. Pertijs, K. A. A. Makinwa, and J. H. Huijsing, “A CMOS smart temperature sensor with a batch-calibrated inaccuracy of ±0.25℃ (3σ) from -70 ℃ to 130 ℃ ,” ISSCC Dig. Tech. Papers, pp. 342–343, Feb. 2009.
[33]K. Souri, Y. Chae, and K. Makinwa, “A CMOS temperature sensor with a voltage-calibrated inaccuracy of ±0.15℃ (3σ) from -55 to 125 ℃ ,” in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 2012, pp.208–209.
[34]J. Shor, et al., “Ratiometric BJT-Based Thermal Sensor in 32nm and 22nm Technologies,” ISSCC Dig. Tech. Papers, pp. 210-211, 2012.
[35]王進賢、何宗武，碩士論文，民國103年七月。臺灣嘉義縣：中正大學電機工程研究所。
[36]William James DALLY, “Power-supply-insensitive buffer and oscillator circuit,” U.S. Patent 0120047 A1, May. 16, 2013.