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研究生:陳家源
研究生(外文):Chan Ka-Un
論文名稱:1.25GbpsCMOS數位發射機
論文名稱(外文):A 1.25 Gbps CMOS Digital Transmitter
指導教授:吳介琮
指導教授(外文):Wu Jieh-Tsorng
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1999
畢業學年度:87
語文別:中文
論文頁數:59
中文關鍵詞:串列傳輸發射機杷鎖迴路
外文關鍵詞:serial linktransmitterphase lock loop
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本篇論文描述一個 3.3 伏特, 每秒能發射 1.25 兆位元的 CMOS 數位發射機,它包含有十個相位的相鎖迴路時脈產生器, 十對一多工器, 以及一能驅動50歐姆的輸出驅動器. 此系統在此的主要應用於高速串列傳輸, 把 125 MHz 10 位元的並列資料, 轉換成串列資料.
十個相位的相鎖迴路時脈產生器是本論文的核心, 由電壓控制振盪器, 相位/頻率偵測器和電荷充放式濾波器所組成,且加入一相位平均化電路, 能減小相位誤差, 故能產生 10 個規則排列的精確相位, 且平均分佈於一個週期內, 壓控振盪器是從 0.2 MHz 到 250 MHz, 中心頻率為 125 MHz.
此相鎖迴路系統是使用 0.35mm 1P4M CMOS 製程技術下線生產.
電源電壓為 3.3V, 整個面績為 1800×1800 mm2,
消耗功率約 160 mV.

This thesis described the design of a 3.3 V CMOS digital transmitter that transmits 1.25 gigabit per second, which is composed of a 10 phase phase-lock-loop(PLL) clock generator, a 10 to 1 multiplexer and an output driver which drives 50 ohm. The digital transmitter is used in the high speed serial link which converts parallel data into serial data.
The 10 phase PLL clock generator is composed of a voltage-controlled oscillator(VCO), a phase/Frequency Detector(PFD), a charge pumping filter(CP), and a phase average circuit, due to minimize phase jitter. The PLL generates 10 outputs with equally-spaced phases spanning the entire oscillation period. The ouput frequency of the VCO varies from 0.2 MHz to 250 MHz, and the central frequency is 125 MHz.
The digital transmitter has been fabricated with a 0.35mm 1P4M CMOS technology. Total power consumption is about 160 mW under a 3.3 V supply.

1緒論………………………………………………1
1.1研究動機…………………………………………1
1.2論文組織…………………………………………3
2十個相位的相鎖迴路時脈產生器………………5
2.1簡介………………………………………………5
2.1.1 相鎖迴路的抖動分析……………………………5
2.2十個相位的壓控振盪器…………………………7
2.2.1 電流模式電路簡介………………………………9
2.2.2 對稱性負載………………………….…………..10
2.2.3 壓控振盪器之延遲單元電路設計………………11
2.2.4 壓控振盪器之延遲單元偏壓電路設計…………12
2.2.5 相位平均化電路設計…………………………….15
2.2.6 壓控振盪器佈局及模擬結果……………………20
2.3相位/頻率偵測器之設計…………………………20
2.3.1 簡介………………………………………………20
2.3.2 相位/頻率偵測器的邏輯架構與電路…………24
2.3.3 相位/頻率偵測器的偏壓電路與輸入緩衝器…..27
2.3.4 相位/頻率偵測器與輸入緩衝器佈局…………..28
2.4電荷充放電路之設計……………………………28
2.4.1 簡介………………………………………………28
2.4.2 傳統的電荷充放電路……………………………30
2.4.3 新型電流模式的電荷充放電路…………………32
2.4.4 電荷充放電路佈局及模擬結果…………………35
2.5 相鎖迴路系統參數設計及總結…………………..36
2.5.1 相鎖迴路系統簡介………………………………36
2.5.2 濾波器設計及系統參數…………………………39
3十對一多工器與輸出驅動器……………………43
3.1簡介………………………………………………43
3.2十對一多工器……………………………………43
3.2.1 簡介………………………………………………43
3.2.2 十對一多工器電路介紹…………………………46
3.2.3 十對一多工器偏壓電路…………………………47
3.2.4 十對一多工器佈局及模擬結果…………………49
3.3輸出驅動器………………………………………49
3.3.1 電路介紹…………………………………………49
3.4佈局與模擬………………………………………50
4結論與建議………………………………………55
4.1結論………………………………………………55
4.2建議將來研究方向………………………………55

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