臺灣博碩士論文加值系統

本論文實現一個10位元每秒八億取樣的電流式數位類比轉換器，基於考量電路的線性度和晶片面積大小，編碼方面採用二位元權重碼和溫度碼所組成，電流源電晶體採用面積分析去克服製程變動，為了抑制突波增進電路的動態效能，訊號同步方面改採用正反器方式實現。
晶片實現使用TSMC 0.18μm 1P6M CMOS製程，電流式數位類比轉換器在模擬結果取樣頻率為800MS/s下，當輸入訊號為102MHz時，無雜訊動態範圍(SFDR)可達到61.9dB，微分非線性度(DNL)介於+0.454/-0.258LSB、積分非線性度(INL)介於+0.310/-0.206LSB，整體晶片面積為1.458 x 1.248 mm2，總必v消耗20.98mW。
有了採用面積去克服製程變動的經驗後，接著我們提出一個新的前景校正方式，只需要以6bit來分析電流源電晶體面積，電路效能可達到12bit的線性度，校正概念為控制電流源電晶體body端的電壓，改變原先Vth0電壓，進而校正Id電流。晶片操作電壓在1.8V、解析度為12bit、取樣頻率達250MHz，是個具有小面積特性的數位類比轉換器。

A 10-bit 800M-Sample/s current-steering digital-to-analog converter(DAC) is designed in this thesis. Considering both circuit linearity and chip area, binary-weighted code and thermometer codes are used in encoding. Area analysis is used to overcome process variations for current source transistors. In order to reduce glitch and enhance dynamical performance of the DAC, filp-flops are utilized in signal synchronization.
The chip is implemented in TSMC 0.18μm 1P6M CMOS technology. Simulation results show that the SFDR of the current-steering DAC with an input frequency of 102MHz under sampling frequency of 800MHz is 61.9dB. The DNL is about +0.454/-0.258LSB and INL is about +0.310/-0.206LSB. The total area is 1.458 x 1.248 mm2. The total power consumption is 20.98mW.
With the experience of the area analysis to overcome process variations, then a new foreground calibration technique is proposed. Only 6 bits are for required analyzing current source transistors area and overall 12-bit linearity could be reached after calibration. The key concept of the calibration scheme is to control the body voltages of the current source transistors. The actual threshold voltage varied accordingly and hence the drain current Id is calibrated. The DAC operates with supply voltage of 1.8V, and can achieve 12-bit resolution at sampling frequency of 250MHz. Furthermore, this DAC demonstrates small-area characteristic.

摘要 i
Abstract ii
誌謝 iv
目錄 v
圖目錄 ix
表目錄 xiii
第一章 緒論 1
1.1研究背景 1
1.2研究動機與目的 1
1.3論文架構 2
第二章 數位類比轉換器簡介與架構 3
2.1 數位類比轉換器簡介 3
2.1.1解析度(Resolution) 4
2.1.2偏移誤差 (Offset Error) 5
2.1.3增益誤差 (Gain Error) 6
2.1.4突波 (Glitches) 6
2.1.5穏定時間 (Settling time) 7
2.1.6差動非線性誤差 (Differential nonlinearit error DNL) 7
2.1.7累積非線性誤差 (Integral nonlinearity error INL) 8
2.1.8無寄生動態範圍 (SFDR) 9
2.1.9單調性 (Monotonicity) 9
2.1.10有效位元 (ENOB) 10
2.1.11訊號雜訊比 (Signal-To-Noise Ratio，SNR) 10
2.1.12訊號雜訊失真比 (Signal-to-Noise and Distortion Ratio，SNDR) 10
2.1.13總諧波失真 (Total Harmonic Distortion，THD) 11
2.2 數位類比轉換器架構 12
2.2.1電阻串列式數位類比轉換器 (Resistor-String D/A Converter)[4] 12
2.2.2數位解碼器之電阻串列式數位類比轉換器 13
2.2.3二級電阻串列式數位類比轉換器[5] 14
2.2.4二位元權重電阻式數位類比轉換器 15
2.2.5減少電阻值階梯式數位類比轉換器 15
2.2.6 R-2R電阻階梯式數位類比轉換器 16
2.2.7電荷重新分佈開關電容數位類比轉換器 17
2.2.8二位元權重電流式數位類比轉換器 18
2.2.9溫度計碼電流式數位類比轉換器 18
2.2.10溫度計式編碼 19
2.2.11分段式數位類比轉換器 21
第三章 電流式數位類比轉換器 22
3.1 電流式數位類比轉換器(Current-Steering DAC)電路架構 22
3.1.1單位電流源 24
3.1.2電流源面積分析 25
3.1.3拴鎖電路 28
3.1.4電流源開關組的時脈饋入 33
3.1.5梯度誤差 33
3.1.6二位元和三位元的溫度計解碼器 35
3.1.7 二進位電流制 ( Binary Weighted ) 37
3.1.8 溫度計結構式 (Thermometer Coded) 37
3.2 Forground Calibration DAC電路設計 38
3.2.1校正方法 38
3.2.2逐漸趨近式暫存器電路設計 41
3.2.3電流比較器[18] 44
第四章 Current-Steering DAC整體電路模擬 45
4.1 Current-Steering DAC 的Post-Simulation模擬結果 45
4.1.1 靜態參數 45
4.1.2動態參數 46
4.1.3 Current-Steering DAC模擬結果與比較 48
4.2 Current-Steering DAC整體電路佈局圖 50
4.3 Forground Calibration DAC的 Pre-Simulation模擬結果 51
4.3.1靜態參數 51
4.3.2 Forground Calibration DAC模擬結果與比較 53
第五章 量測結果 55
5.1 量測方法 56
5.1.1電源調節電路(Power Regulator Circuit) 58
5.1.2電流式數位類比轉換器測試板 60
5.2 量測結果 62
第六章 結論與未來展望 65
參考文獻 66

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