臺灣博碩士論文加值系統

近年來由於行動電子產品的蓬勃發展使得非揮發性快閃記憶體快速成長，然而未來的繼續微縮卻因目前頗高的操作電壓而充滿著嚴峻的挑戰。本論文提出一個創新概念的蕭特基多位元電荷捕捉式快閃記憶體作為未來非揮發性記憶體的可行方案，利用二維模擬軟體展示其於寫入、抹除與讀取各操作方式之特性，並探究相應之物理機制，同時發展出載子注入機率之物理模型。
不同於傳統元件的行為，於蕭特基元件中，電子與電洞皆可經由穿隧蕭特基能障而進入通道。利用此雙向導通之特性，當施加正閘極電壓時，蕭特基快閃記憶體可利用特殊的源極端將高能電子注入方式進行寫入動作；同理，當施加負閘極電壓時便可以引起熱電洞於汲極端注入進行抹除動作。此獨特的寫入與抹除方式可以有效避免在一般元件中閘極與源極/汲極間的電壓衝突效應，達成低電壓與高效能之寫入抹除操作。
在讀取的動作上，多位元蕭特基快閃記憶體可利用電荷捕捉式記憶體之標準的雙向反轉讀取方式來進行。雖然蕭特基元件之雙向導通特性可能造成記憶體讀取上之可能誤判，但是經由元件參數及讀取動作之深入探討，蕭特基能障記憶體具備獨特的穩定性。而在微縮上，因為其特殊之電子注入寫入及電洞注入抹除行為，使其儲存載子之分布相對緊密與勻稱；更因蕭特基接面之獨特能障，於元件微縮時可有效抑制短通道效應，使其成為未來極具優勢之多位元記憶體之候選者。

Chapter 1 Introduction 1
1.1 Floating-Gate Flash Memory 2
1.2 Charge Trapping Flash Memory 3
1.3 Evolution of Schottky Barrier MOSFETs 5
1.4 Objectives and Organization 7
Chapter 2 Physics and Modeling in Numerical Simulations 13
2.1 Device Structure of Schottky Barrier Cell 13
2.2 Schottky Barrier MOS Devices 15
2.3 Schottky Barrier and Conventional MOS Devices 18
2.4 Ambipolar Conduction of Schottky Barrier MOS Devices 20
2.5 Gate Current of Schottky Barrier MOS Devices 21
Chapter 3 Programming and Erasing Operations 28
3.1 Operation Scheme of Multi-Bit Cell 28
3.2 Dependence of Bias conditions 30
3.3 Effects of Material Parameters 34
3.4 Matching of Electron and Hole Distributions 37
3.5 Discussions 38
Chapter 4 Reading Operation 53
4.1 Operation scheme 53
4.2 Dependence of Bias Conditions 56
4.3 Effects of Material Parameters 57
4.4 Spatial Location of Stored Charge 59
4.5 Effects of Bulk Voltage and Schottky Barrier Height 60
4.6 Discussions 62
Chapter 5 Cell Scalability 78
5.1 Programming and Erasing Operations 78
5.2 Reading Operation and Short-channel Effect 82
5.3 Matching of Electron and Hole Distributions 84
Chapter 6 Modeling of Injection Probability 100
6.1 Gate-Controlled Electric Field 100
6.2 Probability Model 105
6.3 Results and Discussions 106
Chapter 7 Conclusions 116
Reference 118

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