臺灣博碩士論文加值系統

目前各界所重視的第三代行動通訊系統共有數種不同的規格, 如CDMA-2000, W-CDMA, ...等. 雖然整體的架構不盡相同, 但它們的最高傳輸速度都超過1Mbps, 在如此高的速度之下, 一個重要的課題就是如何能維持傳輸品質, 因此這些規格都是以Turbo code為其編解碼系統, 因為在近年
的研究中證明Turbo code可於相當低的SNR下仍能使數位通訊系統具有低的位元錯誤率. 而Turbo code的一個特點是其decoder的複雜度較encoder高出許多, 所以本論文將焦點集中在decoder.
在目前可用的演算法中, MAP(maxmimum a posteriori probability)的解碼錯誤率是較低的, 但複雜度與計算量也是最高的, MAP本身的結構使得電路在流程的控制上不太容易, 而本論文的目的就在於以MAP為基礎去設計出解碼硬體電路, 主要重點有三:
1. 探討數種不同的電路架構, 這些架構都是以MAP演算法為基礎, 但計算的流程與資料的流向有所不同, 而一般在意的是它們的面積, 解碼速度與記憶體用量. 我們將會提出一個名為Two-Beta的電路架構, 其在面積與速度的考量上, 較其他在本論文中提到的架構要好.
2. 藉由軟體模擬的結果來觀察MAP演算法中一些細節對於解碼錯誤率的影響, 我們由此可以看出一些面積, 速度, 與錯誤率之間的trade-off關係, 以提供其他設計者一個參考.
3. 以電路去實現出deinterleaver, 以取代之前以sram去實現的作法, 如此可以節省相當的記憶體面積.

Turbo codes, due to its excellent capability of maintaining low bit error rate (BER) under high transmission speed and low SNR environment, are adopted in various 3GPP standards for mobile communication systems, such as CDMA 2000, WCDMA, .., etc. Recently, many research efforts have been directed toward developing efficient algorithms, architectures, and VLSI circuits for implementing the much more complicated turbo code decoder. Among many decoding algorithms, the MAP (maximum a posteriori probability) algorithm is the one with the lowest bit-error-rate and also the highest complexity. In this thesis, the focus is on the design and implementation of a high efficient MAP-based turbo decoder. All the designs have been verified using simulation as well as FPGA implementation on Altera Flex 10K100 and EP20K1000E. The main contributions of the thesis can be divided into three parts:
1. Several VLSI MAP decoder architectures with different operation control and data flow together with techniques for improving decoder circuit efficiency are proposed and analyzed. A comparison of their throughput (decoding speed) and cost (circuit area and memory usage) indicates that the proposed Two-Beta architecture has the fastest decoding speed of exceeding 4.5 Mbps and reasonable cost.
2. The relation between some parameters in the MAP algorithm, such as correcting methods of max* operation and noise variance, and BER of decoding are also analyzed with extensive simulations. Trade-offs between the circuit cost, speed, and BER can be made based on these simulation results.
3. A novel design of deinterleaver circuit is also proposed which can drastically reduce the memory usage and hence save VLSI chip area.

國立清華大學電機工程學系 碩士論文 快速渦輪解碼器的設計與實現 91 王子健

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