跳到主要內容

臺灣博碩士論文加值系統

(216.73.217.9) 您好!臺灣時間:2026/10/20 04:13
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:林韋名
研究生(外文):Wei-Ming Lin
論文名稱:射頻發射器之類比前端電路設計
論文名稱(外文):Analog Front End for CMOS RF Transmitter
指導教授:黃弘一
指導教授(外文):Hong-Yi Huang
學位類別:碩士
校院名稱:輔仁大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:中文
論文頁數:103
中文關鍵詞:射頻、發射器、鎖相迴路、脈波寬度控制電路、功率放大器
外文關鍵詞:RF、transmitter、PLL、PWCL、power amplifier
相關次數:
  • 被引用被引用:0
  • 點閱點閱:251
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
  本篇論文描述一個應用在無線通訊系統之射頻發射器,其中主要分為三大部分,鎖相迴路、脈波寬度控制電路以及發射器前端電路,應用頻率範圍在315~916MHz,訊號調變方式為ASK與Audio (AM)模式,訊號輸出功率為100mW。
  鎖相迴路採用整數型除32之架構,提供發射器315~916MHz之中心頻率,由於壓控振盪器使用了源極隨耦器作為內部電源,使得振盪器核心操作在標準電壓之下,其後經由電壓位移為全擺幅訊號,因而鎖相迴路中心頻率之Duty cycle偏離50%,在此提出一個新型互補式脈波寬度控制電路用來校正鎖相迴路輸出訊號之Duty cycle。
  發射器前端電路利用模式選擇電路決定操作為ASK或Audio模式,ASK模式時,模式選擇電路輸出較大振幅之中心頻率,並輸入數位邏輯訊號,使混波器操作在非線性區(輸出飽和);Audio模式時,模式選擇電路輸出較小振幅之中心頻率,並輸入Audio訊號,使混波器操作在線性區,混波器執行ASK或Audio基頻訊號與中心頻率調變與升頻的工作,最後藉由三級功率放大器將輸出訊號功率放大,透過天線將訊號送出。
  電路設計與佈局採用TSMC 0.35μm 1P4M CMOS製程,鎖相迴路與脈波寬度控制電路為第一個晶片佈局,面積為670×920μm2,發射器前端電路則為第二個晶片佈局,面積為3762.1×1766.1μm2,考量到發射器前端電路以0.35μm製程來實現特性並不是相當理想,因此實際只有鎖相迴路與脈波寬度控制電路佈局下線實作,晶片量測發現鎖相迴路之充放電幫浦輸出點可能有短路的情形發生,使得迴路並不能正常工作,但由壓控振盪器仍能正常工作,並輸入一Duty cycle非50%的訊號到脈波寬度控制電路,經由校正可得出一50% Duty cycle之輸出訊號,量測頻率為900MHz,其訊號抖動程度為峰到峰42ps。

 This thesis described a RF transmitter used in wireless communication system. The transmitter has three main parts, included phase-locked loop, pulsewidth control loop and transmitter front-end circuits. It’s operating frequency range is 315~916MHz. The modulation are ASK and Audio (AM) mode. The signal output power is 100mW.
 The architecture of phase-locked loop is integer and divided by 32 type. It was used to provide the center frequency of the transmitter. Due to use source follower as the internal power supply of the voltage-controlled oscillator making the operating voltage supply of the voltage-controlled oscillator core circuit under the standard power supply and then output a full-swing signal using level-shift. Therefore, the duty cycle of the center frequency of the phase-locked loop is away from 50%. Here proposed a novel mutual-correlated pulsewidth control loop circuit to adjust the duty cycle of the output signal of the phase-locked loop.
 The transmitter front-end circuits utilized a mode-select circuit to determine operating at ASK or Audio mode. In ASK mode, the mode-select circuit outputs the large amplitude of the center frequency and was assigned digital logic signal to mixer making it operates at non-linear region (output saturation); in Audio mode, the mode-select circuit outputs the small amplitude of the center frequency and was assigned audio signal to mixer making it operates at linear region. The mixer executes the modulation and upconversion of the ASK or audio baseband signal and the center frequency. Finally, the power of the output signal was amplified and signal was transmitted by antenna.
 The TSMC 0.35μm 1P4M CMOS process is used for the circuit designs and layout. The phase-locked loop and the pulsewidth control loop is the first chip layout, the area is 670×920μm2. The transmitter front-end circuits is the second chip layout, the area is 3762.1×1766.1μm2. Due to the performances of the transmitter front-end circuits is not good implemented using the 0.35μm CMOS process; only the first chip was fabricated. The charge pump output was found a possible short problem at the chip measurements and results the loop of the phase-locked loop does not converge. However, the voltage-controlled oscillator is still work and outputs a non-50% duty cycle signal to pulsewidth control loop. The pulsewidth control loop adjusts the duty cycle of the signal as 50%, the measured frequency is 900MHz and the peak to peak jitter is 42ps.

目錄
摘要...........................................................i
Abstract......................................................ii
誌謝.........................................................iii
表目錄........................................................vi
圖目錄.......................................................vii
第一章 緒論...................................................1
1.1無線通訊系統簡介............................................1
1.2研究動機....................................................2
1.3射頻發射器基本架構簡介......................................2
1.3.1 Direct-conversion transmitter............................2
1.3.2 Two-step transmitter.....................................4
1.4調變方式....................................................4
1.5鎖相迴路簡介................................................6
1.6 功率放大器簡介.............................................8
1.6.1 Class A功率放大器........................................9
1.6.2 Class B功率放大器.......................................11
1.6.3 Class C功率放大器.......................................13
1.6.4 Class AB功率放大器......................................15
1.6.5 Class D功率放大器.......................................16
1.6.6 Class E功率放大器.......................................17
1.6.7 Class F功率放大器.......................................18
1.6.8 Class S功率放大器.......................................19
1.7 螺旋型電感模型............................................20
1.8阻抗匹配...................................................21
1.9論文組織...................................................24
第二章 鎖相迴路..............................................26
2.1相位頻率檢測器.............................................26
2.2充放電幫浦&低通濾波器......................................29
2.3壓控振盪器.................................................33
2.4除頻器.....................................................35
2.5脈波寬度控制電路...........................................36
2.6鎖相迴路系統響應模擬.......................................38
第三章 脈波寬度控制電路......................................41
3.1 Duty cycle repeater.......................................41
3.2傳統型脈波寬度控制電路.....................................43
3.3低電壓型脈波寬度控制電路...................................51
3.4互補型脈波寬度控制電路.....................................54
3.5脈波寬度控制電路之充放電幫浦...............................63
第四章 發射器前端電路........................................67
4.1壓控振盪器.................................................68
4.2模式選擇電路...............................................69
4.3混波器.....................................................70
4.4三級功率放大器.............................................71
第五章 電路佈局與晶片量測....................................75
5.1鎖相迴路與脈波寬度控制電路佈局.............................75
5.2發射器前端電路佈局.........................................83
5.3電路設計與使用製程分析.....................................90
5.4晶片量測...................................................92
第六章 結論與未來研究方向....................................94
6.1結論.......................................................94
6.2未來研究方向...............................................95
參考文獻......................................................96
簡歷..........................................................99
附件.........................................................100

參考文獻
[1]湯鴻沼, 信號與通訊, 全華科技圖書股份有限公司.
[2]Behzad Razavi, “RF MICROELECTRONICS, ”PRENTICE HALL PTR,1998, ISBN 0-13-887571-5.
[3]Thomas H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits, ”Cambridge University Press 1998, ISBN 0-521-63922-0.
[4]TSMC 0.35μm Technology Datasheets.
[5]袁杰, 高頻通信電路設計-被動網路, 全華科技圖書股份有限公司.
[6]Hee-Tae Ahn and D.J. Allstot, “A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications,” IEEE J. Solid-State Circuits, Vol.35, pp. 450 —454, Mar. 2000.
[7]Christopher Lam and Behzad Razavi, “A 2.6GHz/5.2-GHz frequency synthesizer in 0.4μm CMOS technology,” IEEE J. Solid-State Circuits, Vol.35, pp. 788 —794, May 2000.
[8]Ian A. Young, Jeffrey K. Greason, and Keng L. Wong, “A PLL clock generator with 5 to 100MHz of lock range for microprocessor,” IEEE J. Solid-State Circuits, Vol. SC-27, pp. 1599—1607, Nov. 1992.
[9]David W. Boerstler, “A low-jitter PLL clock generator for microprocessors with lock range of 340-612MHz,” IEEE J. Solid-State Circuits, Vol.34, pp. 513 —519, Apr. 1999.
[10]Guang-Kaai Dehng, Ching-Yuan Yang, June-Ming Hsu, and Shen-Iuan Liu, “A 900-MHz 1-V CMOS frequency synthesizer,” IEEE J. Solid-State Circuits, Vol.35, pp. 1211 —1214, Aug. 2000.
[11]Robert C. Chang and Lung-Chih Kuo, “A new low-voltage charge pump circuit for PLL,” IEEE J. Solid-State Circuits, Vol.34, pp. 790 —804, Jun. 1999.
[12]V. von Kaenel, D. Aebischer, R. van Dongen, C. Piguet, “A 600MHz CMOS PLL microprocessor clock generator with a 1.2GHz VCO,” ISSCC Dig. Of Tech. Papers, pp. 396 —397, Feb. 1998.
[13]Ali Hajimiri and Thomas H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, Vol.34, pp. 717 —724, May 1999.
[14]Ali Hajimiri, Sotitios Limotyrakis, and Thomas H. Lee, “Jitter and phase noise in ring oscillators,” IEEE J. Solid-State Circuits, Vol.34, pp. 790 —804, Jun. 1999.
[15]Ahmed H. Mostafa, Mourad N. El-Gamal, and Ramez A. Rafla, “A sub-1-V 4-GHz CMOS VCO and a 12.5-GHz oscillator for low-voltage and high-frequency application,” IEEE Transactions on Circuits and Systems, Vol.48, pp. 919 —926, Oct. 2001.
[16]Y. Fouzar, M. Sawan, and Y. Savaria, “CMOS wide-swing differential VCO for fully integrated fast PLL,” IEEE Midwest Symp. On Circuits and Systems, pp. 948 —950, Aug. 2000.
[17]M.A. Do, R. Zhao, K.S., and J.-G. Ma, “Fully integrated 10GHz CMOS VCO,” Electronics Letters, Vol.37, pp. 1021—1023, Aug. 2001.
[18]Wei-Min Lin and Hong-Yi Huang, “A low-jitter mutual-correlated pulsewidth control loop circuit,” accepted by IEEE Journal of Solid-State Circuits.
[19]Wei-Min Lin and Hong-Yi Huang, “A low-jitter mutual-correlated pulsewidth control loop circuit,” accepted by IEEE International SOC Conference, 2003.
[20]Kazuyuki Nakamura, Muneo Fukaishi, Yoshinori Hirota, Youetsu Nakazawa and Michio Yotsuyanagi, “A CMOS 50% duty cycle repeater using complementary phase blending,” IEEE Symposiums on VLSI Circuits Digest of Technical Papers, pp. 48 —49, 2000.
[21]Fenghao Mu and Christer Svensson, “Pulsewidth control loop in high-speed CMOS clock buffers,” IEEE Transcations on Solid-State Circuits, Vol.35, pp. 134 —141, Feb. 2000.
[22]Jinn-Shyan Wang and Po-Hui Yang, “Low-voltage CMOS pulsewidth control loop using push-pull charge pump,” Electronics Letters, Vol.37, pp. 409—411, Nov. 2001.
[23]Po-Hui Yang and Jinn-Shyan Wang, “Low-voltage pulsewidth control loop for SOC applications,” IEEE J. Solid-State Circuits, Vol.37, pp. 1348 —1351, Oct. 2002.
[24]Jinn-Shyan Wang, Chang-Fen Hu and Yi-Ming Wang, “An a11-digital pulse-width locked loop,” M.S. Thesis, Department of Electrical Engineering National Chung Cheng University, Taiwan, 2002.
[25]Chung-Yu Wu and Shuo-Yuan Hsiao, “The design of a 3-V 900-MHz CMOS bandpass amplifier,” IEEE J. Solid-State Circuits, Vol. 32, pp. 159-168, Feb. 1997.
[26]Shuo-Yuan Hsiao and Chung-Yu Wu, “A parallel structure for CMOS four-quadrant analog multiplier and Its application to a 2-GHz RF downconversion mixer,” IEEE J. Solid-State Circuits, Vol. 33, pp. 859-869, Feb. 1998.
[27]Hong-Sing Kao and Chung-Yu Wu, “A compact CMOS 2V low-power direct-conversion quadrature modulator merged with quadrature voltage-controlled oscillator and RF amplifier for 1.9GHz RF transmitter applications,” IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland.
[28]Ravi Gupta, Brian M. Ballweber, and David J. Allstot, “Design and optimization of CMOS RF power amplifiers,” IEEE J. Solid-State Circuits, Vol.36, pp. 166 —175, Feb. 2001.
[29]Jiin-Chuan Wu and Shiao-Min Hsu, “Design of CMOS mixer,” M.S. Thesis, Department of Electronics Engineering College of Electrical Engineering and Computer Science National Chiao-Tung University, Taiwan, 1997.
[30]Adel S. Sedra, Kenneth C. Smith, “Microelectronic circuit,” Forth Edition, Oxford University Press, IBSN 0-19-511690-9.
[31]Behzad Razavi, “Design of analog CMOS integrated circuits, ”PRENTICE HALL PTR,1998, ISBN 0-13-887571-5.
[32]Neil H.E. Weste Kamran Eshraghian, “Principles of CMOS VLSI design - A System Perspective,” Second Edition, Addison — Wesley Publishing Company, ISBN 0-201-53376-6.
[33]M. Morris Mano, Charles R. Kime, “Logic and computer design fundamentals,’’ International Edition, Prentice Hall, IBSN 0-13-206780-3.
[34]Peter V.O’neil, “Advanced engineering mathematics,” Fourth Edition, An International Thomson Publishing Company, ISBN 0-534-94320-9.
[35]James W. Nilsson and Susan A. Riedel, “Electric circuits,” Fifth Edition, ISBN 957-626-829-4.

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
1. 33.黃美文、吳盛、劉旭榮,「臺灣企業導入電子商務發展情形之探討」,大仁學報,第18期,2000,第365-378頁。
2. 8.吳宛芳,「開放大陸人士來臺觀光之商機評析」,元大京華投資資訊,2001年10月,第15-18頁。
3. 16.侯望倫、周宣光,「產業電子化知識服務體系設計雛議」,產業論壇,產業經濟與資訊服務中心/工業技術研究院,第3卷第2期,2002,第133-164頁。
4. 14.林梓聯,「充滿生機魅力的田園生活」,農政與農情,1998年10月號,第31-36頁。
5. 10.吳乾正,「農園的民宿經營」,農業經營管理會訊,第27期,2001,第10-11頁。
6. 6.何郁如、湯秋玲,「墾丁國家公園住宿服務現況之研究」,戶外遊憩研究,第2期,1989,第51-62頁。
7. 42.鄭健雄,「民宿經營之道」,農業經營管理會訊,第27期,2001,第6-9頁。
8. 43.鄭詩華,「農村民宿之經營管理」,戶外遊憩研究,第5期,1990,第13-24頁。
9. 46.賴杉桂,「電子商務行銷策略發展趨勢之研究」,今日會計,第79期,2000,第85-98頁。
10. 48.戴旭如,「臺灣民宿農莊之規劃與經營管理∼由嘉義農場之個案說起」,臺灣經濟,第197期,1993,第69-73頁。
11. 53.蘇聖義,「效率e 上乘的電子化建置:企業內電子化實例-敬鵬工業企業資源規劃系統」,工業自動化電子化,第3 卷,1990,第31-34頁。