臺灣博碩士論文加值系統

低壓降線性穩壓器常使用在各種電子產品上，特別是在可攜式電子產品。本論文的研究重點為設計一款低壓降線性穩壓器，電路上利用了PTAT正溫度係數與CTAT負溫度係數互相抵銷的方法，解決了一般傳統低壓降線性穩壓器溫度漂移的問題；並且利用線性電壓補償與回授網路，實現全負載範圍內的穩定以及提供一個穩定的參考電壓，同時降低應用成本，確保系統的可靠性。
本電路設計基於線性穩壓器的基本原理和TSMC 0.35um CMOS製程，輸入電壓是1.8V，最高輸出電壓為1.5881V，最大輸出電流為100mA，利用Hspice、Laker、Cadence、Calibre軟體工具進行模擬、佈局和驗證。驗證結果說明，負載電流為100mA時漏失電壓為211.9mV，其他性能指標均滿足設計要求。

Low dropout (LDO) linear regulators are widely used in various electronic products, especially in the portable electronic products as an important driver. This research focuses on the design of a low-dropout linear regulator, where the positive temperature coefficient of a PTAT (Proportional To Absolute Temperature) voltage source and the negative temperature coefficient of a CTAT (Complementary To Absolute Temperature) current source cancel each other to solve the temperature drift problems in the traditional LDO regulator. Using line voltage compensation and feedback network achieves stability in the whole load range and provides a stable reference voltage while reducing application costs and ensuring system reliability.
The low dropout linear regulator design is based on TSMC 0.35um CMOS process. The input voltage is 1.8V, the maximum output voltage is 1.5881V, and the maximum output current is 100mA. The whole chip has been designed, simulated, laid out and verified using the EDA software, such as Hspice, Laker, Cadence and Calibre. The validation results indicate when load current is 100mA, the dropout voltage is 211.9mV, and other performance indicators meet the design requirements.

致謝I
摘要II
ABSTRACT III
目次IV
圖次VI
表次X
第壹章 緒論1
1.1 研究動機與目的1
1.2 論文組織2
第貳章 線性穩壓器與切換式轉換器之介紹與參數分析3
2.1 低壓降線性穩壓器介紹4
2.2 低壓降線性穩壓器之參數定義6
2.2.1 BJT與MOSFET導通元件6
2.2.2輸入輸出電壓差7
2.2.3靜態電流8
2.2.4線性調節率10
2.2.5負載調節率12
2.2.6電源效率13
2.2.7暫態響應13
2.2.8供應電源排斥比16
第參章 溫度補償電路17
3.1 溫度補償電路介紹17
3.2 正溫度係數PTAT參考電流源電路18
3.3 線性電壓補償電路20
3.4 負溫度係數CTAT參考電壓電路23
3.5 誤差放大器電路24
第肆章 低壓降線性穩壓器設計29
4.1 低壓降線性穩壓器之設計29
4.2 低壓降線性穩壓器完整架構30
4.3 輸出入電壓差32
4.4 線性調節率34
4.5 電源排斥比36
4.6 暫態響應38
4.7 負載調節率39
4.8 低壓降線性穩壓器之整體表現40
第伍章 結論41
5.1 結論41
5.2 未來展望41
參考文獻42

[1] Aminzadeh, H.; Nabavi, M.R.; Serdijn, W.A., “Low-dropout voltage source: an alternative approach for low-dropout voltage regulators, ” IEEE Tarns. Circuits Syst. II, vol.61, no.6, pp.413,417, June 2014
[2] B. Razavi, Design of Analog CMOS Integrated Circuit, McGraw-Hill, Boston, 2001.
[3] G. A. R. Mora, and P. E. Allen, “Optimized frequency-shaping circuit topologies for LDOs,” IEEE Tarns. Circuits Syst. II, vol.45, pp.703-708, Jun. 1998.
[4] G. A. Rincon-Mora, “Current efficient, low voltage, low drop-out regulators,” Ph.D. Dissertation Georgia institute of technology, Nov.1996.
[5] C. S. Wu, “Low-cost dual output voltage level low-dropout linear regulator using a novel MUX-base adjustable reference voltage generator,” Department of Electrical Engineering, National Cheng King University, MS Thesis, Jan. 2008.
[6] S. Heng, and P. Cong-Kha, “A low-power high-PSRR low-dropout regulator with bulk-gate controlled circuit,” IEEE Tarns. Circuits Syst. II, pp. 245-249, vol. 57, Apr. 2010.
[7] H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi and K. Sakui, “A CMOS bandgap reference circuit with sub-1-V operation, ” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 670~674, May 1999.
[8] P. Malcovati, F. Maloberti, M. Pruzzi and C. Fiocchi, “Curvature compensated BiCMOS bandgap with 1 V supply voltage, ” in Proc. ESSCIRC, pp. 7~21 Sept. 2000.
[9] J. Doyle, Young Jun Lee, Yong-Bin Kim, H. Wilsch and F. Lombardi, “A CMOS sub bandgap reference circuit with 1-v power supply voltage, ” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 252~255, Jan. 2004.
[10] C.-J. Park, M. Onabajo, and J. Silva-Martinez, “External capacitor-less low drop-out regulator with 25 dB superior power supply rejection in the 0.4–4 MHz range,” IEEE J. Solid-State Circuits, vol. 49, no. 2, pp. 486–501, Feb. 2014.
[11] C. Zhan and W.-H. Ki, “An output-capacitor-free adaptively biased low- dropout regulator with subthreshold undershoot-reduction for SoC,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 5, pp. 1119–1131, May 2012.
[12] Y.-T. Wang, R. L.Geiger, and S.-C. Huang, “Threshold-based voltage reference with pn- junction temperature compensation,” in Proc. IEEE MWSCAS, Aug. 2-5 2009, pp. 156–159.