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研究生:陳彥彬
研究生(外文):Yan-Bin Chen
論文名稱:以無電鍍鎳方式接合銅柱之研究
論文名稱(外文):Development of Interconnects by Electroless Nickel Plating
指導教授:高振宏高振宏引用關係
指導教授(外文):C. Robert Kao
口試委員:顏怡文吳子嘉何政恩
口試委員(外文):Yee-Wen YenAlbert T. WuCheng-En Ho
口試日期:2015-07-24
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:材料科學與工程學研究所
學門:工程學門
學類:材料工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:104
語文別:英文
論文頁數:51
中文關鍵詞:無電鍍鎳圓頂銅柱覆晶接合銅柱陣列Triton X-100
外文關鍵詞:electroless nickel platingdome-shaped copper pillarflip chip bondingcopper pillar arrayTriton X-100
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隨著封裝技術的進步,封裝尺寸與線寬也逐步縮小。而在微焊點的尺度下以焊錫連接的方式將會面臨的一些挑戰使可靠度下降。因此本實驗將研究低溫且無焊錫的接合方式。由於無電鍍具有選擇性上鍍、厚度均一且屬於低溫製程的特性,所以本研究採用無電鍍鎳的方式接合銅柱。
本實驗的電鍍溫度控制在74 ℃,而電鍍時間則依照銅柱間的距離而定。無電鍍後的試片將會由光學顯微鏡及電子顯微鏡分析。實驗中也測試不同的無電鍍鎳條件,包括在無電鍍液中添加Triton X、在無電鍍製程中使試片旋轉以及使用圓頂銅柱。從沒有任何添加的無電鍍鎳試片結果可發現鎳紙上鍍在試片的四周靠近間隙入口的位置。
藉由添加Triton X-100界面活性劑能夠使位於試片中心的銅柱能順利上鍍,但從拋光的試片可發現鎳鍍從中有不規則狀的孔洞及隙縫存在。為了增加鍍液在試片中的物質交換效率,也嘗試在無電鍍的過程中使試片旋轉。有添加旋轉的試片在銅柱接合處的鎳鍍層中有規則的碟柱孔洞出現。除了使用圓柱型的銅柱進行無電鍍之外,在實驗中也有採用圓頂型的銅柱。使用圓頂形銅柱的無電鍍鎳接合的結果可分為三類。第一種情況是在接合處形成連續且橫跨整根銅柱的隙縫。第二種情況則為大部分的鎳層都接合,只有小部分有不連續的隙縫產生。第三種,則是鎳鍍層完全接合,沒有縫隙產生。


As the progress of the electronic packaging, the critical dimension continues to reduce in size. At the scale of micro bump, solder joints would encounter some issues affecting its reliability. A low temperature process of interconnection technology of chips without using solder was researched in this paper. Because of selective plating and uniformity in thickness, electroless nickel plating was applied to pillar interconnection in flip chip bonding.
Copper pillars were interconnected by electroless nickel plating at 74 ℃ and the plating time was decided by the distance between two pillars. The samples were inspected and analyzed by optical microscope (OM) and scanning electron microscope (SEM). Different methods were tested to optimize the electroless nickel bonding, including Triton X-100 addition, sample rotation and dome-shaped pillar. The results of electroless nickel plating of aligned chips without any additive showed that nickel only plated on the surface near the entrances of the gap.
By adding Triton X-100 to the plating bath, the pillar array located at the central of chip could be plated by nickel, however, the cross-sectional images showed some irregular voids trapped and seams in the nickel plating layer. To increase the mass transfer of reactants in the gap, rotation was applied to the sample while electroless nickel plating. A void with disk-like shape could be observed in the plated nickel layer of the sample been rotated. Not only flat-topped pillar but also dome-shaped pillar were tested in this experiment. According to the results of electroless nickel plating using dome-shaped pillars with sample rotation, the plated nickel layer showed three different cases of bonding, first, a seam across the whole pillar existed in the nickel layer, second, some discontinuous seams remained in the nickel layer, third, a seam-less bonding.


致謝....................................................i
中文摘要................................................ii
ABSTRACT..............................................iii
CONTENTS................................................v
LIST OF FIGURES.......................................vii
Chapter 1 Introduction..................................1
Chapter 2 Literature reviews............................4
2.1 Electroless nickel plating on copper pillar.........4
2.2 Electroless copper plating on copper pillar........10
Chapter 3 Experimental.................................18
Chapter 4 Results and discussion.......................23
4.1 Electorless nickel plating on flat-topped pillars..23
4.2 Electroless nickel plating on flat-topped pillars with Triton X-100 addition.............................26
4.3 Electroless nickel plating on flat-topped pillars with rotation and Triton X-100 addition................29
4.3.1 Electroless nickel plating with rotation speed 57 rpm....................................................29
4.3.2 Electroless nickel plating with rotation speed 133 rpm....................................................33
4.3.3 Electroless nickel plating with rotation speed 196 rpm....................................................36
4.4 Electroless nickel plating on dome-shaped pillars with rotation and Triton X-100 addition................38
4.5 EDX analysis.......................................46
Chapter 5 Conclusion...................................48
REFERENCE..............................................50


[1]K. Zeng, K. N. Tu, “Six cases of reliability study of Pb-free solder joints in electronic packaging technology,” Mater. Sci. Eng., R, 38, pp. 55-105, 2002.
[2]H. Y. Chuang, C. Robert Kao, “Critical Concerns in Soldering Reactions Arising from Space Confinement in 3-D IC Packages,” IEEE T Device Mat. Re., vol. 12, no. 2, June 2012.
[3]A. L. X. Jiang, L. C. Ming, J. C. Y. Gao, T. K. Hwee “Pillar Bump Technology and Integrated Embedded Passive Devices,” in Proc. ICEPT, Shanghai, CHINA, 2006.
[4]W. Koh, B. Lin, J. Tai, “Copper Pillar Bump Technology Progress Overview,” in Proc. ICEPT-HDP, Shanghai, CHINA, 2011, pp.1133-1137.
[5]T. Wang, F. Tung, L. Foo and V. Dutta, “Studies on A Novel Flip-Chip Interconnect Structure – Pillar Bump,” in Proc. Electron. Comp. Technol. Conf., Orlando, FL, USA, 2001, pp. 945–949.
[6]T. Osborn, A. He, H. Lightsey, and P. A. Kohl. “All-Copper Chip-to Substrate interconnects: Bonding, testing, and design for electrical performance and Thermo-Mechanical reliability.” In Proc. ECTC, Orlando, FL, USA, 2008, pp.67-74.
[7]H. C. Koo, P. Kohl, “Copper Electroless Bonding of Dome-Shaped Pillars for Chip-to-Package Interconnect,” J. Electrochem. Soc., vol. 158 no. 12, D698-D703, 2011.
[8]H. C. Koo, P. Kohl, “Affect of Anneal Temperature on All-Copper Flip-Chip Connections Formed via Electroless Copper Deposition,” IEEE T COMPON PACK, vol. 2, no. 1, January, 2012.
[9]J. Lee, D. M. Fernandez, M. Paing, Y. C. Yeo, and S. Gao, “Electroless Ni plating to Compensate for Bump Height Variation in Cu-Cu 3-D Packaging,” IEEE T COMPON PACK, vol. 2, no. 6, pp.964-970, June, 2012.
[10]A. He, T. Osborn, S. A. B. Allen and P. A. Kohl, “Low-Temperature Bonding of Copper Pillars for All-Copper Chip-to-Substrate Interconnections,” Electrochem. Solid-State Lett., vol. 9, no. 12, C192-C195, 2006.

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