|
[1]K. Zeng, K. N. Tu, “Six cases of reliability study of Pb-free solder joints in electronic packaging technology,” Mater. Sci. Eng., R, 38, pp. 55-105, 2002. [2]H. Y. Chuang, C. Robert Kao, “Critical Concerns in Soldering Reactions Arising from Space Confinement in 3-D IC Packages,” IEEE T Device Mat. Re., vol. 12, no. 2, June 2012. [3]A. L. X. Jiang, L. C. Ming, J. C. Y. Gao, T. K. Hwee “Pillar Bump Technology and Integrated Embedded Passive Devices,” in Proc. ICEPT, Shanghai, CHINA, 2006. [4]W. Koh, B. Lin, J. Tai, “Copper Pillar Bump Technology Progress Overview,” in Proc. ICEPT-HDP, Shanghai, CHINA, 2011, pp.1133-1137. [5]T. Wang, F. Tung, L. Foo and V. Dutta, “Studies on A Novel Flip-Chip Interconnect Structure – Pillar Bump,” in Proc. Electron. Comp. Technol. Conf., Orlando, FL, USA, 2001, pp. 945–949. [6]T. Osborn, A. He, H. Lightsey, and P. A. Kohl. “All-Copper Chip-to Substrate interconnects: Bonding, testing, and design for electrical performance and Thermo-Mechanical reliability.” In Proc. ECTC, Orlando, FL, USA, 2008, pp.67-74. [7]H. C. Koo, P. Kohl, “Copper Electroless Bonding of Dome-Shaped Pillars for Chip-to-Package Interconnect,” J. Electrochem. Soc., vol. 158 no. 12, D698-D703, 2011. [8]H. C. Koo, P. Kohl, “Affect of Anneal Temperature on All-Copper Flip-Chip Connections Formed via Electroless Copper Deposition,” IEEE T COMPON PACK, vol. 2, no. 1, January, 2012. [9]J. Lee, D. M. Fernandez, M. Paing, Y. C. Yeo, and S. Gao, “Electroless Ni plating to Compensate for Bump Height Variation in Cu-Cu 3-D Packaging,” IEEE T COMPON PACK, vol. 2, no. 6, pp.964-970, June, 2012. [10]A. He, T. Osborn, S. A. B. Allen and P. A. Kohl, “Low-Temperature Bonding of Copper Pillars for All-Copper Chip-to-Substrate Interconnections,” Electrochem. Solid-State Lett., vol. 9, no. 12, C192-C195, 2006.
|