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With the progress of digital signal processing, many
complicate functions can be realized by modern VLSI technology.
However, for analog signal processing, many existing
solutions are still not cost and power effective. The main
objective of thisthesis is to develop the low-voltage low-power
circuit design techniques for analog front-end application.
The proposed circuits are based on the heterodyne receiver
architecture. RF/IF analog-front-end functions are included
for pager receiver applications. Since they are for wireless
communication requirements, power dissipation is a determinant
factor on exploring and developing the circuit structures.
At RF stage, a 280MHz low-noise amplifier and a 280MHz to
10.7MHz mixer are introduced. A shunt-feedback type
amplifier followed by an open-drain buffer is proposed as
LNA. It provides moderate gain of 18dB S21 and 3.65dB NF with
power consumption of 4.6mW. For mixer design, a single-balanced
structure is employed. It provides 9.4dB conversion gain
while dissipates 3mW power for 2-V supply operation.
In 455KHz IF signal processor, a 3-stage limiting amplifier and
a quadrature demodulation are included. A feedforward type
offset cancellation structure is proposed to eliminate the
need of external capacitors. A quadrature with external phase
shifting network and an on-chip phase detector shows a good
frequency discrimination performance under low voltage
operation. The input dynamic range is 72dB and the
demodulation constant is 20mV/KHz. The total circuits
consume 2.3mW.
For 10.7MHz IF signal processing, a seven-stage limiting
amplifier and a RSSI areinvolved. The seven-stage structure gets
a good compromise between speed and power performance.
Each gain stage is a source-coupled pair with a folded diode
load. It can meet the DC-coupled requirements for 2-V operation.
The proposed limiting amplifier can achieve smaller than
-78dBm sensitivity. For logarithmic RSSI stage, a current
mode rectification and summation are proposed to achieve the
required linear approximation. The measured results indicate
that the dynamic range can be wider than 70dB. The power
consumption is 6.2mW. The
proposed circuits are all implemented using a 0.6um digital CMOS
technology. The power supply is 2-V. Measured results
demonstrate good agreements with the original design concepts.
Although the proposed circuit structures are mainly for
pager system, it is believed that many techniques can be applied
to otherwireless RF/IF signal processings that need low-voltage
low-power operations.
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