臺灣博碩士論文加值系統

延遲鎖定迴路因為為一階恆穩定回授系統面積小好設計外，還有雜訊在電壓控制延遲嚴上不會累積雜訊，輸出時脈抖動小的優點，被用來當成時脈產生器的使用上如:記憶體介面、液晶顯示器、無線電傳輸系統...等，成為近幾年來受歡迎的電路架構。然而，改善鎖定時間長和因為雜訊產生的非理想抖動是設計延遲鎖定迴路重要的課題，本文分別針對此問題，提出改善方法。
本延遲所定迴路，利用電壓控制延遲線一個週期延遲時間固定的特性，設計一個時脈頻率預測器，在延遲所定迴路的迴授系統運作之前，改變初始電壓到接近鎖定電壓的位準，再進行延遲所定迴路的迴授系統運作，利用充電幫浦的校正到鎖定電壓，縮短所定時間，使得電路能有快速鎖定的功能。除此之外，為了降低輸出時脈的抖動，本延遲鎖定迴路使用自動抖動校正電路產生一個延遲與兩個相位偵測器組合成一個假相位偵測器，縮小系統的抖動區域，得到較低的輸出時脈抖動。
本延遲鎖定迴路採用CMOS 0.18um 1P6M 標準製程，核心面積為0.77x0.84mm2，功率消耗為29mW操作在400MHz，可鎖範圍為150MHz~550MHz，鎖定時間為低於9cycles，peak-to-peak jitter為2.9ps操作在400MHz。

With a first order system and the noise would not accumulate in the voltage controlled delay line (VCDL), delay-locked loop has advamtages such as: easy to design, having small aarea and good jitter performance for clock generator.So it is becoming a popular architecture used in memory intergface, LCD, wireless communication system... etc. However, the locking time and the jitter caused by non-ideal effect are important topics for delaylocked loop. In this paper, we proposed an auto jitter calibration delay-locked loop with fast locking feature to overcome these two problems.
The proposed delay-locked loop, causing the voltage controlled delay line, VCDL's "A fixed latency of one clock cycle,"[9], we design a frequency estimator circuit to change the initial voltage at the almost locking level to accelerate the locking time before the DLL's feedback system of charge pump's fine tuning until the DLL is locked. In addition, the proposed DLL using an auto jitter calibration to produce a little delay that is combining two phase frequency detectors to suppress the jitter area, and the output jitter is smaller.
The proposed DLL is fabricated in CMOS 0.18μm 1P6M technology. The core area is 0.77x0.84mm2 and the power dissipation is 29m at 400MHz. The locking range is 150MHz~550MHz and the locking time is <9 cycles. The Peak-to-Peak Jitter is 2.9ps at 400MHz.

第一章　　緒論 1
1.1 背景 1
1.2 研究動機 2
1.3 論文概要 2
第二章 延遲鎖定回路設計 5
2.1 延遲鎖定迴路種類 5
2.1.1 全類比式電路: 5
2.1.2 全數位式電路: 5
2.1.3 類比數位混合式電路: 5
2.2 傳統的延遲鎖定迴路架構介紹 6
2.2.1 鎖定範圍 7
2.2.2 系統穩定性分析 11
2.2.3 時脈錯離 15
2.3 延遲鎖定迴路基本電路 18
2.3.1 相位偵測器(PD) 18
2.3.2 充電幫浦(Charge Pump)與迴路濾波器(Low Pass Filter) 21
2.3.3 電壓控制延遲線(VCDL) 22
2.3.3.1 RC 時間常數控制之延遲元件 22
2.3.3.2 可變電容式之延遲元件 23
2.3.3.3 餓電流(Current-Starved)控制之延遲元件 24
2.3.3.4 差動對稱性負載之延遲元件 24
第三章 時脈抖動 27
3.1時脈抖動的定義與分類 27
3.1.1 週期對週期時脈抖動(Jcc) 28
3.1.2 週期時脈抖動(Jpi) 30
3.1.3 長期性時脈抖動(Jlong ) 31
3.2時脈抖動直方圖 32
3.3時脈抖動的來源 33
第四章 自動時脈振顫校正之延遲鎖定迴路 37
4.1 自動時脈振顫校正之延遲鎖定迴路架構 39
4.1.1 頻率預測 40
4.1.3 抖動校正(Jitter Calibration) 47
4.2 電路描述 49
4.2.1 延遲原件( Delay Cell) 49
4.2.2 改變初始電壓電路(Changing Initial Voltage Circuit, CIVC) 50
4.2.3 含起始控制電路相位偵測器 (Phase Frequency Detector with Start-Controlled Circuit) 50
4.2.4 開關控制電路 (Switch Controlled Circuit) 52
4.2.5 充電幫浦 (Charge Pump) 53
4.3 設計流程 53
4.4 模擬結果 55
4.5 量測環境 59
4.6 預計量測結果 62
4.7 總結 65
第五章 結論與未來研究方向 67
參考文獻 69

[1] B. Razavi, Monolithic phase-locked loops and clock recovery circuits: theory and design, IEEE press, 1996.
[2] F. M. Gardner, “Charge-pump phase-lock loops,” IEEE Trans. Commun., vol. 28, no. 13, pp. 1894-1858, Nov. 1980.
[3] R. E. Best, Phase-locked loops: theory, design and applications, New York: McGraw-Hill, 1998.
[4] K. H. Cheng, Y. L. Lo “A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs,” IEEE ESSCIRC, Grenoble, France, pp. 189-192, Sep. 2005.
[5] K. H. Cheng, C. W. Su, M.J. Wu, and Y. L. Chang “A wide-range DLL-based clock generator with phase error calibration,” IEEE ICECS., Malta, pp. 798-801, Aug. 2008.
[6] Hoyos, S., Tsang, C.W., Vanderhaegen, J., Chiu, Y., Aibara, Y., Khorramabadi, H., Nikolic, B., “A 15 MHz – 600 MHz, 20 mW, 0.38 mm2, fast coarse locking digital DLL in 0.13μm CMOS,” IEEE ESSCIRC, Edinburgh, Scotland, UK, pp. 90-94, Sep. 2008.
[7] Chien-Hung Kuo, and Yi-Shun Shih, “A Frequency Synthesizer Using Two Different Delay Feedbacks,” IEEE International Symposium on Circuits and Systems, Kobe, Japan, pp.2799-2802, May. 2005.
[8] C. H. Kuo, M. F. Lin, and C. H. Chen, “A multi-band delay-locked loop with fast-locked and jitter-bounded features,” IEEE ASSCC, Fukuoka, Japan, pp. 441-444, Nov. 2008.
[9] H. H. Chang, J. W. Lin, S. I. Liu, “A wide-range delay-locked loop with a fixed latency of one clock cycle,” IEEE J. Solid-State Circuits, vol. 37, no.8 , pp. 1021-1027, Aug. 2002.
[10] R. Jacob Baker, CMOS Mixed-Signal Circuit design, Wiley Inter-Science, 1998
[11] D. H. Wolaver, Phase-locked loop circuit design, Prentice Hall, 1991
[12] L. Wang, L. Liu, and H. Chen, “An Implementation of Fast-Locking and Wide-Range 11-bit Reversible SAR DLL,” IEEE Trans. Circuit Syst. II, Exp. Brief, vol. 57, no. 6, pp. 421-425, June. 2010.
[13] F. R. Liao, and S. S. Lu, “A Programmable Edge-Combining DLL With a Current-Splitting Charge Pump for Spur Suppression,” IEEE Trans. Circuit Syst. II, Exp. Brief, vol. 57, no. 12, pp. 946-950, Dec. 2010.
[14] Md. Sayfullah, B. Rolnd, Arpad L. Scholtz, “Jitter Analysis of a Mixed PLL-DLL Architecture,” IEEE ICECE, Dhaka, Bangladesh, pp. 750-754, Dec. 2008.
[15] K. Chung, J. Koo, S. W. Kim, and C. Kim, “An Anti-Harmonic, Programmable DLL-Based Frequency Multiplier for Dynamic Frequency Scaling,” IEEE ASSCC, Jeju, Korea, pp. 276-279, Nov. 2007.
[16] Y. H. Tu, H. H. Chang, C. L. Hung, and K. H. Cheng, “A 3GHz DLL-Based Clock Generator with Stuck Locking Protection,” IEEE ICECS, Athens, pp. 106-109, Dec. 2010
[17] K. H. Cheng, W. B. Tang, and C. M. Ying, “A Dual-Slop Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop,” IEEE Trans. Circuit Syst. II, Exp. Brief, vol. 50, no. 11, pp. 892-896, Nov. 2003.
[18] Soh Lip-Kai, Mohd-Shahiman Sulaiman, and Zubaida Yusoff, “A Fast-Lock Dual Charge Pump Analog DLL using Improved Phase Frequency Detector,” IEEE VLSI-DAT, Hsinchu, Taiwan, pp. 1-5, Apr. 2007.
[19] K. H. Cheng, and Y. L. Lo, “A Fast-Lock Wide Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator,” IEEE Trans. Circuit Syst. II, Exp. Brief, vol. 54, no. 7, pp. 561-565, July. 2007.
[20] B. G. Kim, and L. S. Kim, “A 250-MHz-2-GHz wide-range delay-locked loop,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1310-1321, Jun. 2005.
[21] T. C. Lee, and K. J. Hsiao, “ The design and analysis of a DLL-based frequency synthesizer for UWB application, ” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1245-1252, Jun. 2006.
[22] G. Kim, M. K. Kim, B.S. Chang, W. Kim, “ A low-voltage, low power CMOS elay element, ” IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 966-971, July. 1996.
[23] M. G. John and E. L. Hudson, “A variable delay line PLL for CPU-coprocessor synchronization, ” IEEE J. Solid-State Circuits, vol. 23, no. 5, pp. 1218-1223, Oct. 1998.
[24] T. H. Su, “Design of a CMOS Delay-Locked Loop based programmable frequency multiplier,” Master Thesis, National Dong-Hwa University, July. 2005.
[25] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-bias techniques,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov. 1996.
[26] “Jitter in Clock Sources,” Vectron International.
[27] F. Herzel, and B. Razavi, “A Study of Oscillator Jitter Due to Supply and Substrate,” IEEE Transactions on Circuits and System II, vol. 46, pp. 56-62, Jan. 1999.
[28] N. Soo, “Jitter Measurement Technique,” Pericom Application Brief AB36, Nov. 2000.
[29] A. H. Chan, and G. W. Robert, “A Jitter Characterization System Using a Component-Invariant Vernier Delay Line,” IEEE Transactions on VLSI System, vol.12, pp. 79-94, Jan. 2001..
[30] W. M. Lin, K. F. Teng, and S. I. Liu, “A Delay-Locked Loop with Digital Background Calibration,” IEEE ASSCC, Taipei, Taiwan, pp. 317-320, Nov. 2009.