臺灣博碩士論文加值系統

隨著多媒體的廣泛運用，視訊應用也愈來愈趨多元化。在目前的視訊壓縮標準中，移動估計的運算量佔了絕大部份的比例，所以需設計專門的硬體來處理。本篇論文提出了一個適用於MPEG－4模組化全搜尋移動估計架構；在這個架構下，對於不同視訊應用的需求，例如區塊、搜尋範圍的大小，以及不同的操作頻率，可以藉由運算單元模組間的連接與堆疊所組成的運算單元陣列來支援。如此一來，在系統的規格有所變動時，系統整合者可以很容易地獲得符合需求的移動估計器，而省去重新設計新硬體的時間與人力。在MPEG－4視訊壓縮標準中，採用了物件的概念；在執行移動估計時，除了原本的區塊對應方法，物件邊緣的區塊需使用多邊形對應的方法，我們所提出的架構可以支援這個功能。由於無線通訊的蓬勃發展，減低晶片的功率消耗也成為一重要的課題。移動估計的功率消耗主要有兩個來源，一為在資料路徑中的大量運算，另一則是頻繁的記憶體存取與資料傳輸。在運算單元中，藉由簡單的誤差比較判斷，減少不必要的電路切換，來達到節省功率消耗的目的；在資料存取的方面，我們利用階層性記憶體配置的概念，在晶片中加入了緩衝器，降低移動估計器與外部記憶體存取的次數，減少功率的消耗。晶片的實作是採用0.35微米單層多晶矽四層金屬層的CMOS製程，晶片大小為3.5 x 3.5 mm2，工作頻率設定在50MHz，可達到MPEG－4核心面第一層的即時要求；而在50MHz下消耗的功率約為140mW。

In this paper, we present a scalable module-based architecture for block matching motion estimation algorithm of MPEG-4. The basic module is one set of processing elements based on one-dimensional systolic array architecture. To support various applications, different modules of processing elements can be configured to form the processing element array to meet the requirements, such as variable block size, search range and computation power. And this proposed architecture has the advantage of few I/O port counts. Based on eliminating unnecessary signal transitions in the processing element, power dissipation of datapath can be reduced to about half without decreasing the picture quality. In addition, for data-dominant video applications like motion estimation, the power consumption is also influenced significantly by the architecture of memory. In order to reduce the power consumption due to the memory accesses of external memory, we propose four schemes of memory hierarchy according to different levels of data reuse. The evaluations of all schemes are parameterized, and designers can easily derive a better scheme under reasonable hardware resources and power consumption. Considering of system integration, the influence of I/O bandwidth between motion estimation unit and system bus is also discussed in the paper.

1 Introduction 1
1.1 Video Coding System ........................ 2
1.2 Motion Estimation Algorithm .................... 3
1.3 Operation Reduction in Motion Estimation Algorithms ...... 5
1.4 Organization of This Thesis . .................... 6
2 MPEG-4 Video Coding Standard 8
2.1 Video Object Plane and Shape Coding . . ............. 9
2.2 Padding Process . . . ........................ 13
2.3 Polygon Matching in Motion Estimation . ............. 13
2.4 Functions of Motion Estimation/Compensation . . . . ...... 16
3 Previous Architecture of Motion Estimation 22
3.1 Systolic Array . . . . ........................ 22
3.2 Scalable and Flexible Architecture . . . . ............. 23
3.2.1 Programmable Design . . . . . . ............. 25
3.2.2 Scalable and Reconfigurable Architecture . . . ...... 26
4 Scalable Module-Based Architecture 29
4.1 Motion Estimation Core . . .................... 29
4.2 Processing Element Module Architecture ............. 29
4.3 Architecture Reconfiguration .................... 34
4.3.1 Case I : larger block size . . . . . ............. 34
4.3.2 Case II: increasing search range . ............. 35
4.3.3 Case III: lower operation frequency . . . . . . ...... 36
4.4 PE with Power-saving Operation . . . . . ............. 36
4.5 Operation in Advanced Prediction Mode . ............. 38
4.6 Strategy of Memory Hierarchy . . . . . . ............. 39
4.6.1 Data reuse between different rows of candidates in one
column of a block (Scheme A) . . ............. 41
4.6.2 Data reuse between adjacent columns of candidates in a
block (Scheme B) . . .................... 43
4.6.3 Data reuse between adjacent blocks in one row of block
(Scheme C) . ........................ 43
4.6.4 Data reuse between different rows of block (Scheme D) . 43
4.7 System Integration Consideration . . . . . ............. 45
4.8 Memory Architecture ........................ 46
4.8.1 Memory bank partition . . . . . . ............. 46
4.8.2 Method of data update . . . . . . ............. 51
4.9 Chip Comparison and Discussion . . . . . ............. 53
5 Implementation 56
5.1 Design Flow . . . . . ........................ 57
5.2 Testing Consideration ........................ 58
5.3 Chip Layout and Specification . . . . . . ............. 60
6 Conclusion 62

[1] S. S. S. Fukunaga, Y. Nakaya and T. Nagumo, JTC1/SC29/WG11, N3093a,
MPEG-4 Video Verification Model version 15.0. Maui: ISO/IEC, 15 ed.,
1998.
[2] JTC1/SC29/WG11, N2502a, Generic Coding of Audio-Visual Objects: Vi-sual
14496-2, Final Draft IS. Atlantic City: ISO/IEC, 1998.
[3] H.263 version 2: Video Coding for Low Bit Rate Communication. SG16:
ITU-T Recommendation, 2 ed., 1997.
[4] T. Koya, K. Iinuma, A.Hirano, Y. IiJima, and T. Ishiguro, “Motion compen-sated
interframe coding for video conferencing,” in Proceedings of National
Telecommunication Conference, pp. G.5.3.1—G.5.3.5, 1981.
[5] M. Ghanbari, “The cross-search algorithm for motion estimation,” IEEE
Transactions on Communications, vol. 38, no. 7, pp. 950—953, 1990.
[6] B. Natarajan, V. Bhaskaran, and K. Konstantinides, “Low-complexity block-based
motion estimation via one-bit transforms,” IEEE Transactions on Cir-cuits
and Systems for Video Technology, vol. 7, no. 4, pp. 702—706, 1997.
[7] Z. He and M. L. Liou, “Reducing hardware complexity of motion estima-tion
algorithms using truncated pixels,” in IEEE International Symposium
on Circuits and Systems, pp. 2809—2812, 1997.
[8] K.-M. Yang, H. Fujiwara, Y. Ishida, and M. Maruyama, “A flexible motion-vector
estimation chip for real-time video codecs,” in Proceedings of the
Custom Integrated Circuits Conference, pp. 17.5.1—17.5.4, 1990.
[9] S.-I. Uramoto, A. Takabateke, M. Suzuki, H. Sakurai, and M. Yoshimoto, “A
half-pel precision motion estimation processor for NTSC-resolution video,”
in Proceedings of the Custom Integrated Circuits Conference, pp. 11.2.1—
11.2.4, 1993.
[10] H.-M. Jong, L.-G. Chen, and T.-D. Chiueh, “Parallel architectures of 3-step
search block-matching algorithm for video coding,” in Proceeding of IEEE
International Symposium on Circuits and Systems, pp. 209—212, 1994.
[11] M. J. Chen, L. Chen, K.-N. Cheng, and M. C. Chen, “Efficient hybrid
tree/linear array architectures for block-matching motion estimation al-gorithms,”
in Proceedings of IEE Vision, Image and Signal Processing,
pp. 217—222, 1996.
[12] G. K. Yeh, Y.-W. Lu, and J. B. Burr, “A low-power video motion estimation
array processor,” in Symposium on VLSI Circuits Digest of Technical Papers,
pp. 162—163, 1996.
[13] M. Mizuno, Y. Ooi, N. Hayashi, J. Goto, M. Hozumi, K. Furuta,
A. Shibayama, Y. Nakazawa, O. Ohnishi, S.-Y. Zhu, Y. Yokoyama,
Y. Katayama, H. Takano, N. Miki, Y. Senda, I. Tamitani, and M. Yamashima,
“A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power mo-tion
estimation and clocking,” IEEE Journal of Solid-State Circuits, vol. 32,
no. 11, pp. 1807—1997, 1997.