臺灣博碩士論文加值系統

本論文旨在設計一適用於VDSL/VDSL2網路系統之CMOS數位發射機，其操作頻率為200MHz，並採用倍取樣率轉換技術。此發射端電路主要包含有12位元200MHz倍取樣率之數位類比轉換器，以及整合二階濾波器之電流模式全差動線驅動器兩個部份，並採用TSMC 0.18μm 1P6M CMOS製程技術來實現。

VDSL (Very High-bit-rate Digital Subscriber Line)技術使用最高達30MHz訊號頻寬，於短距離的用戶環路上，其資料傳輸可達到最高100Mbps的雙向對稱速率。其上下行傳輸的高資料速率特性，允許用戶使用電話網路的銅線傳輸，連結至最近的光纖網路節點。

為了達到高資料傳輸速率的需求，本論文提出一倍取樣率架構的電流切換式12位元數位類比轉換器。其工作頻率為200MHz，於倍取樣率的工作模式下，可達到等效的400MHz資料轉換速率，其差動輸出電流訊號可達最大4095μA及最高30MHz的類比訊號頻率範圍。

為了滿足VDSL標準的發射端頻譜規範，須使用發射端濾波器以濾除數位類比轉換器的高頻諧波。本論文採用的倍取樣率技術可使主要高頻諧波出現頻率向外推延兩倍，其與訊號頻寬間有更大的過渡頻帶，其結果僅需使用二階濾波器即可滿足發射端的頻譜要求。本論文使用一整合於線驅動器的二階發射端濾波器，以產生30MHz限制頻寬。線驅動器電路利用電流回授補償以及電容前饋方法，以抑制諧波失真問題，並提高線性度。本線驅動器在1.8V的供應電壓下，能驅動100Ω輸出端負載，與2Vpp的電壓訊號振幅。

This thesis describes the chip implementation of a 200MHz/double sampling-rate CMOS digital transmitter based on VDSL system specification. This digital transmitter is composed of a 12-bit, 200MHz digital-to-analog converter (DAC) operated in the proposed double sampling-rate structure, and a fully differential current-mode line driver integrated with a 2nd-ordered transmitting filter. The digital transmitter had been fabricated with the TSMC 0.18μm 1P6M CMOS technology.

VDSL (Very High-Bit Rate Digital Subscriber Line) technology permits the transmission of asymmetric and symmetric data rate up to 100Mbps for upstream and downstream direction on twisted copper pairs using a signal bandwidth up to 30MHz. It can be deployed from fiber-optic connected cabinets located near the customer premises.

For such high-speed applications, the digital-to-analog converter adopts the switch-current mode architecture with a double sampling-rate operation. Under 200MHz clock frequency, the digital-to-analog converter can reach the equivalent 400MHz conversion rate. The simulation of 12-bit DAC shows that the maximum output current is 4095μA, and the conversion signal bandwidth is up to 30MHz.

To conform the bandwidth requirements of VDSL/VDLS2, a transmitting filter is used after the DAC stage to filter the high-frequency harmonics. With the DAC double sampling-rate operation mode, a 2nd-ordered filter is satisfactory in the bandwidth performance. The line drive circuit integrates a transmitting filter and a current-feedback amplifier with capacitor-feedforward compensation to reach high linearity and low harmonic distortion. According to the simulation result, the output voltage of the proposed line driver is 2Vpp at differential load of 100Ω.

摘　要 i
ABSTRACT ii
誌 謝 iii
目錄 iv
表目錄 vii
圖目錄 viii
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 3
1.3 論文架構 4
第二章 數位類比轉換器 5
2.1 簡介 5
2.1.1數位類比轉換器規格之定義 6
2.2 電阻式與電容式數位類比轉換器介紹 8
2.3 電流切換式數位類比轉換器介紹 9
2.3.1 二進位制數位類比轉換器 9
2.3.2 等電流源數位類比轉換器 10
2.3.3 區段式數位類比轉換器 11
2.3.4 倍取樣率等電流源數位類比轉換器 12
2.4 區段式數位碼最佳化之配置 13
2.5 切換式電流源單元 16
2.5.1 串接式電流源輸出阻抗 16
2.5.2 擁有抗製程變因之偏壓電流源 17
2.5.3 開關切換時電流源產生之突波 18
2.5.4 低臨限電壓栓鎖電路 21
2.5.5 低工作電壓之低臨限電壓栓鎖電路 23
2.6 三位元二進位制之數位類比轉換器架構與設計 24
2.7 九位元溫度計碼解碼與矩陣式電流源佈局 25
2.7.1 六位元矩陣式電流源佈局 25
2.7.2 六位元電流源矩陣之溫度計碼解碼器 27
2.7.3 三位元溫度計碼之等電流源電路 30
2.8 十二位元電流切換式數位類比轉換器 30
2.9 使用倍取樣率之電流切換式數位類比轉換器設計 34
2.10 倍取樣率數位類比轉換器模擬結果 38
第三章 線驅動器 44
3.1 線驅動器簡介 44
3.2 線驅動器之基本原理及架構 44
3.2.1 線驅動器之驅動方式 44
3.2.2 全差動電流回授模式之線驅動器 46
3.3 低電壓線驅動器 48
3.3.1 誤差放大器之架構 48
3.3.2 使用誤差放大器架構實現低電壓線驅動器 50
3.4 阻抗匹配之設計 51
3.4.1 阻抗匹配之原理 51
3.4.2 阻抗匹配之電路實現於線驅動器 53
3.4.3 線驅動器共模回授電路實現 55
3.5 利用合成技術來實現低電壓線驅動器 55
3.6 諧波失真抑制之設計 56
3.6.1 電流回授補償電路改善諧波失真之設計 56
3.6.2 前饋電容抑制諧波失真之設計 59
3.7 整合二階濾波器之線驅動器設計 61
3.8 線驅動器之模擬結果 63
第四章 數位發射機 69
4.1 數位發射機之簡介 69
4.2 數位類比轉換器之偏壓電路設計 70
4.2.1 定電流分散式偏壓電路 70
4.2.2 寬擺幅定電導之偏壓電路 71
4.2.3 分散式偏壓電路 74
4.3 線驅動器之偏壓電路設計 75
4.4 數位發射機之模擬結果 75
第五章 結論與未來研究方向 77
5.1 結論 77
5.2 未來研究方向 78
參考文獻 79

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