臺灣博碩士論文加值系統

近幾年來，半導體製程能力進步，使的元件物理特性提高，元件應用在電路的大型積體化已經逐漸成熟。鑿於電路特性及功能需求提升，電路的可靠度評估也在近幾年的學術或業界重要會議中被討論與發表。過去幾年的元件氧化層研究當中，元件的漏電物理機制以及氧化層的可靠度分析，已經大量的被探討和模型化。應用在商業中，操作的生命週期也接著被制訂。本論文以元件可靠度角度出發，廣泛且深度的觀察元件氧化層的衰退機制。從元件衰退後的直流漏電流的量測，到小訊號變化量測，接著再觀察元件操作到頻率高達好幾個GHz的電性衰退特性量測，本論文均有詳細的觀察與討論。廣泛觀察完元件的衰退特性之後，本文提出一個可以銜接SPICE模型的子電路模型，用以描述元件的衰退特性。從直流特性變化，到高頻小訊號衰退變化，都可藉由本文提出的子電路模型來預測。
擁有這個子電路模型後，本文針對一系列可以應用在高頻無線前端系統中重要子電路模組，如低雜訊放大器，頻率混合器，電壓壓控震盪器，以及功率放大器，討論子電路模組當中的元件衰退後，對其相對應子電路模組電路特性的影響。經由實驗數據驗證後的子電路模型，整合成一個操作頻率在5GHz的通訊用無線前端接受器，模擬當其中的子電路模組特性衰退後，對整個無線前端接受器的通用功能影響與變化。更進一步藉由建立的子元件衰退模型設計一個對元件衰退不敏感的高可靠度低雜訊放大器，取代傳統使用的低雜訊放大器，放入前述設計完成的無線前端接受器，再觀察前端接受器特性的變化，證明本文所提出的子電路模型可以用來預測電路本身的可靠度優良與否。
本論文，提出的可以銜接SPICE模型的子電路模型，使電路設計師在選擇電路架構與滿足設計規格的同時，除了保留電路本身遺傳的好特性與交換提升電路特性好處之外，其電路可靠性的良莠也可以在設計電路架構時一併納入考量。

Recently, CMOS device cutoff frequency and maximum oscillation frequency rise to Giga hertz due to the aggressively scaling of semiconductor technologies. Therefore, the highly integrated circuits combing both analog and digital circuits become possible. With the increasing complexity in circuit functionalities, circuit reliability testing and evaluation can be no longer following the conventional method. Conventional reliability assurances through the setting a safe operation region by device lifetime projection is insufficient to meet the demand of today’s IC and nano-scale CMOS technologies. In this dissertation, device degradation mechanisms and oxide reliability are investigated extensively. The device degraded characteristics in both the dc and the small signal characteristics up to Giga hertz are observed. From analyzing the device degradation characteristics, a sub-circuit model for describing the device degradation behavior is proposed. This model predicts both the device dc and small signal behavior in a good agreement with measured data.
Several circuit blocks for RF receiver, such as Low-Noise Amplifier, Mixer, Voltage-Controlled Oscillator and Power Amplifier are designed to discuss the performance shift as a result of degradation after operational stress. A 5GHz CMOS receiver is designed to investigate the effect of each building block on reliability of receiver system. Using the established sub-circuit model, a redesign of the most vulnerable circuit block in a receiver system, the LNA, is performed.
In this dissertation, the reliable evaluation method provides the circuit designers an additional degree of freedom in determining its safe operation conditions and rooms for enhancing both the circuit performance and reliability robustness. The simulated results of the redesigned LNA provide direction for more reliable system design while maintaining the highest circuit performance level.

Abstract (Chinese, English)……………………………………………………. I
Acknowledgements (Chinese, English)……………………………................. III
List of Contents…………………………………………………………………. V
List of Tables……………………………………………………………………... VII
List of Figures…………………………………………………………………….. VIII


Chapter 1 Introduction………………………………………………….. 1
1.1 Motivation………………………………………...................... 1
1.2 Major contributions…………………………………………… 3
1.3 Dissertation organization……………………………………… 3

Chapter 2 Device Degradation Mechanisms and Parameters Shift….. 5
2.1 Device degradation mechanisms in circuit operation………… 5
2.2 Hot carriers stress in a scaled transistor………………………. 5
2.2.1 Carriers injection mechanisms………………………... 8
2.2.2 Device parameters shift after hot carriers stress……… 10
2.3 Fowler-Nordheim stress……………………………………… 11
2.3.1 Physical mechanisms of oxide degradation………….. 11
2.3.2 Basic principles of oxide degradation………………… 14
2.4 Review of Device degradation modeling………..……………. 16

Chapter 3 Experiments and Establishment of Sub-Circuit Degradation model…………………………………………...
36
3.1 Stress setup……………………………………………………. 36
3.2 Measurement setup……………………………………………. 37
3.3 Calibration techniques………………………………………… 37
3.4 De-embedding techniques…………………………………….. 38
3.5 The proposed sub-circuit degradation model…………………. 38
3.6 DC parameters analysis and measurement discussion………... 39
3.7 AC parameters analysis and measurement discussion………... 40

Chapter 4 Reliability Evaluation of Benchmark RF Circuit Blocks…. 59
4.1 Introduction of RF transceiver……………………………....... 59
4.2 The Low-Noise Amplifier……………………………………. 61
4.3 The Voltage-Controlled Oscillator…………………………… 62
4.4 The Mixer…………………………………………………….. 64
4.5 The Power Amplifier…………………………………………. 66

Chapter 5 RFIC System Reliability Evaluation and Design Tradeoff.. 103
5.1 Design of RF building blocks and receiver architecture……… 103
5.2 Impact of circuit block degradation on analog parameters performances………………………………………………….
104
5.3 Impact of circuit block degradation on digital parameters performances…………………………………………………..
105
5.4 System reliability evaluation in Figure-OF-Merits (FOM)…… 106
5.5 Design tradeoff between performance and reliability………… 106

Chapter 6 Conclusions…………………………………………………... 123

Reference ………………………………………………………………… 126
Vita ………………………………………………………………… 136

Chapter 1
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Chapter 5
[5.1] Wei-Cheng Lin; Tsung-Chieh Wu; Yi-Horn Tsai; Ya-Chin King;” Reliability Evaluation and Redesign of LNA,”Microelectronic Reliability, vol.44, pp.1727-1732, 2004.
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