臺灣博碩士論文加值系統

寬頻存取技術，像是各種的數位用戶迴路，藉著混合積體電路的技術來實現。它們提供了在沒有干擾的傳統電話雙絞線上穩定的資料傳送。然而，為了克服銅線的高衰減以及大量回音，類比前端的線路要擁有低雜訊，低失真，精準的頻道濾波和高動態範圍的特性。
本論文呈現了一個適用在超高速數位用戶迴路(VDSL)系統的低電壓雙迴路混合信號的自動增益器之電路設計與實現。自動增益器包含了一個類比的前向信號路徑和一個數位的迴授控制路徑。應用在上/下傳的VDSL系統中，自動增益器的類比部分需要操作在數十百萬赫茲。為了穩定的控制自動增益器的增益，控制路徑利用數位電路的好處，像是不易受製程和溫度的變異的影響。而控制路徑由一個雙迴路的架構，切換在12千赫茲於追踨過程以及5.6千赫茲於穩態。這樣的方式造成了一個快速追踨且雜訊免疫的控制。以0.35um台積電1P4M的數位CMOS製程，自動增益器佔了1.9mm X 2.1mm的面積。根據模擬的結果，在輸入強度從20mVpp到400mVpp都可以提供一個常數量值的輸出並且在小於0.5ms之內收斂。在2V的電壓供應下，類比部分消秏了36mW。數位的回授路徑則在3.3V的電壓供應下流過了3.35mA。

The broadband access technologies, such as various kinds of digital subscriber loops (xDSL) have been implemented with a mixture of IC technologies. They provide robust transport of data on twisted pair without interfering with classical telephone service. However, to overcome high attenuation and large echo of the copper wire, the analog front end circuit (AFE) should possess low noise enhancement, low signal distortion, accurate channel filtering and high dynamic range characteristics.
This thesis presents the design and implementation of a low-voltage dual-loop mixed-signal automatic gain control (AGC) for Very High Speed Digital Subscriber Loop (VDSL) system. The AGC consists of an analog forward signal path and a digital feedback control path. Applied to VDSL system for up/down stream, the AGC calls for its analog parts operating in tens of Mega-hertz frequency. To robustly control the gain of the AGC, the control path takes advantage of digital circuitry that is less susceptible to process and temperature variations. The control path is configured as a dual-loop structure that switches the loop bandwidth to 12kHz in the acquisition state and 5.6kHz in the steady state. This facilitates a faster acquisition process and a noise-insensitive control. Implemented in 0.35um TSMC 1P4M digital CMOS technology, the AGC occupies 1.9mm X 2.1mm chip area. According to the simulation, it provides constant magnitude output for input signal strength from 20mVpp to 400mVpp. The acquisition time is less than 0.5ms. The analog forward path consumes 36mW under 2V supply voltage and the digital feedback path draws 3.35 mA from 3.3V supply voltage.

Chap1. Introduction
Chap2. System Architecture and Designs
Chap3. AGC Consideration in VDSL Receiver Analog Front End
Chap4. AGC Circuit Design
Chap5. VLSI Implementation and Simulation Results
Chap6. Conclusions
Appendix A. Pin Assignment
Appendix B. Test Strategies

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