|
1. S. M. Sze, Semiconductor Devices Physics and Technology, Wiley, 2002. 2. NDL 奈米通訊,http://www.ndl.org.tw/cht/ndlcomm/P5_2/12.htm 3. Xu Qiuxia, Qian He, Yin Huaxiang, Jia Lin, Ji Honghao, Chen Baoqin, Zhu Yajiang, Liu Min, “High performance 70 nm CMOS device and key technologies,” Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on Volume 1, 22-25 Oct. 2001 Page(s):68 - 73 vol.1 4. B.V. Zeghbroeck, Principles of Semiconductor Devices, http://ece-www.colorado.edu/~bart/book/, 2004. 5. BSIM3v3 模型介紹與萃取方式 6. T. Hori, IEDM Tech. Digest, pp.75-78 (1994) 7. Codella, C.F.; Ogura, S., “Halo doping effects in submicron DI-LDD device design,” Electron Devices Meeting, 1985 International Volume 31, 1985 Page(s):230 – 233 8. A. Hori et al., IEDM Tech. Digest, pp.641-644 (1991). 9. Y. Taur and T. H. Ning, Fundamentals of VLSI Devices, pp.189-193, Cambridge University Press (1998). 10. De, I.; Osburn, C.M., “Impact of super-steep-retrograde channel doping profiles on the performance of scaled devices,” Electron Devices, IEEE Transactions on Volume 46, Issue 8, Aug. 1999 Page(s):1711 – 1717 11. S. Wolf, "Silicon Processing for the VLSI Era,” Vol-2, p.338, Lattice Press (1990). 12. S. Wolf, "Silicon Processing for the VLSI Era,” Vol-2, p.340, Lattice Press (1990). 13. Okumura, F., Sera, K., Asada, H., Kaneko, S., Ichinose, H., Naemura, S., Tanaka, K., Yokoi, T., Tani, C., “Ferroelectric liquid-crystal shutter array with poly-Si TFT driver,” Electron Devices, IEEE Transactions on Volume 36, Issue 9, Part 2, Sept. 1989 Page(s):1900 – 1904 14. ITIS產業資訊服務網,2006經濟部技術處產業技術知識服務計畫(ITIS)。 15. R. Jacob Baker, CMOS Circuit Design, Layout and Simulation, Wiley- Interscience, 2005 16. De Rycke, I., De Baets, J., Doutreloigne, J., Van Calster, A., Vanfleteren, J., “The realisation and evaluation of poly-CdSe TFT driving circuits,” Display Research Conference, 1988., Conference Record of the 1988 International 4-6 Oct. 1988 Page(s):70 – 73 17. Fu-Liang Yang, Di-Hong Lee, Hou-Yu Chen, Chang-Yun Chang, Sheng-Da Liu, Cheng-Chuan Huang, Tang-Xuan Chung, Hung-Wei Chen, Chien-Chao Huang, Yi-Hsuan Liu, Chung-Cheng Wu, Chi-Chun Chen, Shih-Chang Chen, Ying-Tsung Chen, Ying-Ho Chen, Chih-Jian Chen, Bor-Wen Chan, Peng-Fu Hsu, Jyu-Horng Shieh, Han-Jan Tao, Yee-Chia Yeo, Yiming Li, Jam-Wem Lee, Pu Chen, Mong-Song Liang, Chenming Hu, “ 5nm-gate nanowire FinFET,” VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on 15-17 June 2004 Page(s):196 – 197 18. Pearce, C.W., Yaney, D.S., “Short-channel effects in MOSFET's,” Electron Device Letters, IEEE Volume 6, Issue 7, Page(s):326 – 328, Jul 1985. 19. 電子工程專輯。 20. 劉傳璽,陳進來,CMOS元件物理與製程整合,五南,民95年。 21. 李明逵,矽元件與積體電路製程,全華科技,民93年。 22. C. Y. Chang and S. M. Sze, ULSI Technology, Mc Graw Hill, 1996. 23. 李俊奇,吳亞芬,沈金鐘譯,線性積體電路,高立出版新科技總經銷,民93年。 24. Mead, Carver, Analog VLSI and Neural Systems, Addison-Wesley, 1989. 25. JV Ashby, RF Fowler and C Greenough, The EVEREST Doping Profile Module, Dec. 1998 26. J. R. Kahng, J. H. Kim, M. S. Jog, andH. S. Yoon, “Scalable Threshold Voltage Model for Deep-Submicrometer MOSFET,” VLSI and CAD, 1999. ICVC '99. 6th International Conference on 26-27 Oct. 1999 Page(s):518 – 521 27. Chi-Chang Wang, Jiin-Chuan Wu, “Efficiency improvement in charge pump circuits,” Solid-State Circuits, IEEE Journal of Volume 32, Issue 6, June 1997 Page(s):852 – 860 28. Hwang-Cherng Chow, Chi-Shun Hsu, “New voltage level shifting circuits for low power CMOS interface applications,” Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on Volume 1, 25-28 July 2004 Page(s):I - 533-6 29. Carver, G.P., “Influence of short-channel effects on dopant profiles obtained from the DC MOSFET profile method,” Electron Devices, IEEE Transactions on Volume 30, Issue 8, Page(s):948 – 954, Aug 1983. 30. Balestra, F., Benachir, M.; Brini, J., Ghibaudo, G. “Analytical models of subthreshold swing and threshold voltage for thin- and ultra-thin-film SOI MOSFETs,” Electron Devices, IEEE Transactions on Volume 37, Issue 11, Nov. 1990 Page(s):2303 – 2311 31. Osman, A.A., Osman, M.A, “Temperature dependent modeling of PD SOI MOSFETs subthreshold conduction,” Devices, Circuits and Systems, 1995. Proceedings of the 1995 First IEEE International Caracas Conference on 12-14 Dec. 1995 Page(s):192 - 195 32. Eraghi, F.A., Chen, J., Solomon, R., Chan, T., Ko, P., Hu, C., “Time dependence of fully-depleted SOI MOSFETs subthreshold current” SOI Conference, 1991. Proceedings., 1991 IEEE International 1-3 Oct. 1991 Page(s):32 - 33 Digital Object Identifier 10.1109/SOI.1991.162842. 33. Balestra, F., Benachir, M., Brini, J., Ghibaudo, G. “Analytical models of subthreshold swing and threshold voltage for thin- and ultra-thin-film SOI MOSFETs” Electron Devices, IEEE Transactions on Volume 37, Issue 11, Nov. 1990 Page(s):2303 – 2311 34. Prof. Philip C. H. CHAN, “Nano Fin Field Effect Transistor (FinFET),” Department of Electrical and Electronic Engineering, and Institute of NanoMaterials and NanoTechnology . 35. Xuejue Huang, Wen-Chin Lee, Kuo, C., Hisamoto, D., Leland Chang, Kedzierski, J., Anderson, E., Takeuchi, H., Yang-Kyu Choi, Asano, K., Subramanian, V., Tsu-Jae King, Bokor, J., Chenming Hu, “Sub-50 nm P-channel FinFET,” Electron Devices, IEEE Transactions on Volume 48, Issue 5, May 2001 Page(s):880 - 886 Digital Object Identifier 10.1109/16.918235.
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