臺灣博碩士論文加值系統

在高效能的VLSI設計中，時脈差異的最小化問題已成為一項非常重要的議題。在此篇論文中，於多電壓模式下使用可調式延遲緩衝器(ADB)於緩衝器時脈樹中以完成時脈差異的最小化。給定緩衝器時脈樹，藉由可調式延遲緩衝器具靈活設定延遲的特性，本篇論文首先提出由下而上的ADB設定以插入ADB，藉由在各功率模式下指定適當的延遲數值於ADB上，使整體的時脈差異達到最小化。考量到ADB可指定的延遲數值是不連續的延遲數值，此篇論文提出有效率的演算法妥善地指定適當的延遲數值於插入的ADB上。此外由下而上的移除演算法被提出，在多電壓模式下將多餘的ADB移除，使ADB數量達到最小化，同時維持界限內時脈差異的大小。和Lim的最佳化演算法比較，實驗結果顯示本論文提出的方法使用更少的執行時間對ADB的數量作最小化，同時在平均上減少8.6%的佈局面積及5.5%的平均延遲時間。

It is well known that clock skew minimization becomes critical in high-performance VLSI designs. In this paper, the assignment of adjustable delay buffers (ADBs) is applied to minimize the clock skew in a buffered clock tree in a multi-voltage mode design. Given a buffered clock tree, based on the assignment flexibility of the delay value on an ADB, bottom-up ADB assignment is firstly proposed to insert ADBs to minimize the clock skew by assigning the delay values of the inserted ADBs for each power mode. Under the consideration of discrete delay values on ADBs, an efficient algorithm is proposed to appropriately assign the feasible delay values on the inserted ADBs. Furthermore, bottom-up ADB elimination is proposed to eliminate the redundant ADBs to minimized the number of the inserted ADBs in a multi-voltage mode design while maintaining the bounded clock skew. Compared with Lim’s optimal algorithm, the experimental results show that our proposed algorithm uses less CPU time to minimize the number of the ADBs, reduced 8.6% of layout areas and 5.5% of the average latency on the average.

摘要………………………………………………………………………………………….i
ABSTRACT………………………………………………………………………………...ii
致謝………………………………………………………………………………………...iii
目錄………………………………………………………………………………………...iv
表目錄………………………………………………………………………………….......vi
圖目錄……………………………………………………………………………………..vii
第一章 簡介…………………………………………………………………………..…1
1.1時脈信號(Clock Signal)的運用…………………………………………………..2
1.2時脈差異(Clock Skew)的問題..…………………………………………………..3
1.3時脈分配網路(Clock Distribution Network) ..……………………………..……..5
1.4多電壓模式(Multi-Voltage Mode)設計…………………………………………...7
1.5時脈拓樸的選擇…………………………………………………………………..9
1.6可調式延遲緩衝器(ADB)常見的元件構造…………………………………….10
第二章 先前相關研究與動機………………………………………………………....14
2.1 Su的研究論文簡介…………………………………………………….………..14
2.2 Lim的研究論文簡介…………………………………………………….………17
2.3 Lin的研究論文簡介……………………………………………………..……....19
2.4 研究動機……………………………………………………………………...…23
第三章 問題描述………………………………………………………........................24
第四章 限制最大延遲時間條件下的ADB設定…………………...….………...……28
4.1由下而上的ADB設定完成時脈差異最小化…..……..…………..…………….29
4.2維持界限內的時脈差異條件下之由上而下ADB分佈…..…………………….40
4.3維持界限內的時脈差異條件下之由下而上ADB移除……..…..……………...45
第五章 放鬆最大延遲時間條件下的ADB設定………………………………...……50
第六章 實驗結果……………………………………….………………………...……53
第七章 結論……………………………………….………………………...........……55
參考文獻……………………………………………………………………………...…...56

[1] S. Tam, S. Rusu, U. N. Desai, R. Kim, J. Zhang, and I. Young, “Clock generation and distribution for the first IA-64 microprocessor,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 11, pp.1545–1552, 2000.
[2] N. A. Kurd, J. S. Barkatullah, R. O. Dizon, T. D. Fletcher, and P. D. Madland, “A multigigahertz clocking scheme for Pentium 4 microprocessor,” IEEE Journal of Solid-State Circuits, Vol. 36, No. 11, pp.1647–1653, 2001.
[3] P. Mahoney, E. Fetzer, B. Doyle, and S. Naffziger, “Clock distribution on a dual-core multi-threaded Itanium-family processor,” International Solid-State Circuits Conference, pp.292–293, 2005.
[4] E. Takahashi, Y. Kasai, M. Murakawa, and T. Higuchi, “A post-silicon clock timing adjustment using genetic algorithms,” International Symposium on VLSI Circuits, pp.13–16, 2003.
[5] J. L. Tsai, D. Baik, C. P. Chen, and K. K. Saluja, “A yield improvement methodology using pre and post-silicon statistical clock scheduling,” International Conference on Computer-Aided Design, pp.611–618, 2004.
[6] J. L. Tsai, L. Zhang, and C. Chen, “Statistical timing analysis driven post-silicon-tunable clock-tree synthesis,” International Conference on Computer- Aided Design, pp.575–581, 2005.
[7] A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, L. Benini, A. Macii, E. Macii and M. Poncino, “Dynamic thermal clock skew compensation using tunable delay buffers,” International Symposium on Low Power Electronics and Design, pp.162-167, 2006.
[8] Y. S. Su, W. K. Hon, C. C. Yang, S. C. Chang and Y. J. Chang, “Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs,” International Conference on Computer-Aided Design, pp.535-538, 2009.
[9] Y. S. Su, W. K. Hon, C. C. Yang, S. C. Chang and Y. J. Chang, “Clock skew minimization in multi-voltage mode designs using adjustable delay buffers,” IEEE Transaction on Computer-Aided Design, Vol. 29, No. 12, pp. 1921–1930, 2010.
[10] K. H. Lim and T. Kim, “An optimal algorithm for allocation, placement and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs,” Asia-South Pacific Design Automation Conference, pp.503-508, 2011.
[11] K. Y. Lin, H. T. Lin and T. Y. Ho, “An efficient algorithm of adjustable delay buffer insertion for clock skew minimization in multiple dynamic supply voltage designs,” Asia-South Pacific Design Automation Conference, pp.825-830, 2011.
[12] K. Y. Lin, H. T. Lin, T. Y. Ho and C. C. Tsai, “Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs,” ACM Trans. on Design Automation of Electronic Systems, Vol. 17, No. 3, Article 34, 2012.
[13] Kao, M.Y.C., Kun-Ting Tsai , Hsuan-Ming Chou and Shih-Chieh Chang, “Post silicon skew tuning: Survey and analysis ,” Asia-South Pacific Design Automation Conference, pp.646-651, 2012.