臺灣博碩士論文加值系統

本論文提出一個直流降壓轉換器的設計，所採用的是TSMC 0.35μm CMOS製程來實現，使用脈衝寬度調變（PWM）和脈衝頻率調變（PFM）雙模式切換來降低輸出漣波和提高轉換效率。
本電路設計是針對以電源供應的輸入在大於3V到小於等於5V為主的產品，輸出會降壓到3V，PWM的操作頻率在1MHz。HSPICE模擬結果顯示，在外部電容10μF和外部電感10μH的情況下，輸出漣波小於15mV，在負載電流150mA時有最佳轉換效率，大約在93%到95%之間。

This thesis proposes a DC-DC buck converter with TSMC 0.35μm CMOS process, using pulse width modulation (PWM) and pulse frequency modulation (PFM) dual mode switching to reduce output voltage ripple and improve conversion efficiency.
This circuit is designed for products with the power supply input voltage from 3V to 5V. The output voltage is stepped down to 3V. The operating frequency of PWM is 1MHz. The HSPICE simulation results show that the output voltage ripple is less than 15mV and the optimum conversion efficiency is from 93% to 95% at 150mA load current with a 10μF external capacitor and a 10μH external inductor.

致謝　i
ABSTRACT　ii
摘要　iii
目錄　iv
圖目錄　vi
表目錄　viii
第一章 緒論　1
1.1 研究動機　1
1.2 章節概述　2
第二章 直流轉換器的基本操作原理　3
2.1 直流轉換器　3
2.1.1 功率電晶體的操作區　4
2.1.2 輸入電壓和輸出電壓的比值關係　6
2.1.3 迴路控制方式　16
2.1.4 電感電流　18
2.2 規格和定義　22
2.2.1 輸出漣波　22
2.2.2 轉換效率　23
第三章 直流降壓轉換器的電路架構和設計說明　24
3.1 電路架構　24
3.2 降壓功率級　26
3.2.1 非重疊緩衝器　28
3.2.2 零電流偵測器　30
3.2.3 遲滯比較器　33
3.2.4 電流感測器　35
3.3 補償器　37
3.3.1 能隙電壓參考電路　41
3.3.2 運算放大器　43
3.4 調變控制器　45
3.4.1 三角波產生器　47
3.4.2 緩啟動電路　49
3.4.3 脈衝寬度調變器　52
3.4.4 脈衝頻率調變器　53
第四章 模擬結果　54
4.1 脈衝寬度調變模式之模擬結果　54
4.1.1 PWM之輸出漣波　55
4.1.2 PWM之轉換效率　60
4.2 脈衝頻率調變模式之模擬結果　61
4.2.1 PFM之輸出漣波　62
4.2.2 PFM之轉換效率　67
4.3 整體電路之模擬結果　68
4.4 文獻比較表　69
第五章 結論與未來研究方向　70
5.1 結論　70
5.2 未來研究方向　71
參考文獻　72

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