臺灣博碩士論文加值系統

在輕薄短小趨勢下所造就出的可攜式影音裝置，引起一般消費大眾的消費浪潮，這股浪潮也造成快閃記憶體的普遍化，正因為這些影音裝置的記憶空間需求一直增大，例如數位相機的畫素的不斷提升，所以造成各製造商不斷開發大容量的快閃記憶體來迎合消費市場的龐大需求，再加上輕薄短小的可攜式影音裝置內建空間本來就有所限制，無法以額外增加更多記憶體的方式來擴充記憶容量，所以必須在單一的封裝尺寸下，製造出比以往更加大記憶容量的記憶卡，而這就必須依賴半導體製造技術能力的提昇。
本研究是以晶片厚度為1.2mil為主，探討如何在快閃記憶體封裝尺寸最小的microSD卡內，作業九層懸臂堆疊產品，以現有設備、材料不變動的前提之下，針對設備硬體及軟體方面做探討，採用田口式品質方法來優化銲線良率及品質，使用反打法，以推球與拉力來量測鋁墊、金線與金球之接合狀況，在90%信心水準的門檻，獲得重要的控制因子，得到相對最佳的製程參數，優化後之推球與拉力分別改善提昇6.94 dB及1.25 dB，並配合使用ANSYS有限元素分析模擬軟體，模擬晶片懸臂銲線時之應力及變形狀況，以驗證九層懸臂堆疊產品之優化結果。

The portable devices created under the trend of lightness, thinness and smallness have triggered a massive wave of buying. This trend has also leaded to the popularity of flash memory. Since these portable devices need larger and larger memory storage space, for example, the enhanced pixel count for digital cameras, manufacturers keep developing flash memories with larger capacities to meet the requirements of the consumer need. However, the internal space of the small form factor portable device is restricted and unable to accommodate more memory components to expand the memory capacity. Therefore, manufacturers have to find a way to expand the memory capacity of the flash memory in a single package, and this relies on the advances of the semiconductor manufacturing technology and capability.
This study takes the die thickness of 1.2 mils as the test object to develop a nine-layer overhang-stacked package for microSD card, the smallest flash memory in size. Without changing the equipment and materials currently used, this study focuses on the investigation of the required equipment and software by applying Taguchi method to optimize the wire bonding yield and quality. Reverse bonding is applied, and ball shear test and wire pull test are used to measure the bonding conditions on bonding pads, gold balls and gold wires. At 90% confidence level, the significant control factors are found and the relatively optimal process parameters are obtained. S/N ratios for ball shear and wire pull after optimization improves by 6.94 dB and 1.25 dB respectively. Moreover, the finite element analysis software ANSYS is used to simulate the stress and deformation during wire bonding on the overhanged chips so as to verify satisfied mechanical strength of the optimization results obtained by the Taguchi method.

中文摘要 …………………………………………………………… I
英文摘要 ………………………………………………………… II
誌謝 ……………………………………………………………… III
目錄 ……………………………………………………………… IV
表目錄 …………………………………………………………… VI
圖目錄 ………………………………………………………… VIII
第一章 緒論 …………………………………………………… 1
1-1 前言 ………………………………………………………… 1
1-2 研究動機及目的 …………………………………………… 2
1-3 快閃記憶體之應用 ………………………………………… 3
1-4 堆疊方式介紹 ……………………………………………… 11
1-5 文獻回顧 …………………………………………………… 19
第二章 3D封裝製程 …………………………………………… 23
2-1 懸臂堆疊封裝製程介紹 …………………………………… 23
2-2 疊晶方式介紹 ……………………………………………… 26
2-3 銲線製程 ………………………………………………… 35
第三章 研究設計與方法……………………………………… 38
3-1 設計方法與流程…………………………………………… 38
3-2 實驗機台與材料條件……………………………………… 38
3-3 收集資料與結果檢測……………………………………… 40
第四章 田口方法及ANSYS模擬分析………………………… 41
4-1 田口方法之實驗設計 ……………………………………… 41
4-2 實驗結果 …………………………………………………… 43
4-3 變異分析 …………………………………………………… 49
4-4 預測及確認 ………………………………………………… 54
4-5 ANSYS模擬分析 …………………………………………… 57
第五章 結論與未來研究方向………………………………… 66
5-1 結論 ………………………………………………………… 66
5-2 未來研究方向 ……………………………………………… 67
參考文獻 ………………………………………………………… 68

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