臺灣博碩士論文加值系統

複晶矽薄膜電晶擁有高場效應遷移率與驅動電流，至今廣泛運用在AMLED、 AMOLED以及、太陽能電池以及快閃記憶體等元件。這幾年也漸漸的發展運用在積體電路建立在玻璃基板上(system on panel SOP)去作為記憶元件與控制端。然而，發現一般傳統型複晶矽薄膜電晶體卻無法提供較好電流驅動的需求以及開關速度。
為了增加複晶矽薄膜電晶體電流驅動與開關速度，過去最有效率的是增加一個閘極。經由雙閘極(Double Gate)對通道的感應能力，驅使主動區可以上下形成感應通道，比原本傳統的薄膜電晶體單一感應通道。然而，雙閘極感應主動區之下，使得原本的汲極端更增加電場，讓元件不理想效應的扭結效應與漏電流更加明顯，這也是元件結構最大的缺點所在。之後，有人提出雙閘極結合了LDD(Light Doped Drain)，而此結構不只保留原來雙閘極結構的高開電流優點，加上擁有較薄的通道閘極更能控制能力更能提升導通電流。且利用淺掺雜 (LDDLight Doped Drain)在元件關閉時有一段阻值去減少漏電流與傳統雙閘極的結構相較下，也能大幅地降低汲極端的高電場。在製程方面此結構必須透過高成本的化學機械研磨(chemical machine polish，CMP)，而所需次數多達兩次造成本花費更高成為此結構的最大致命缺點。
因此，我們從過去前人的研究可以得知閘極對通道其實有密切的關係更有前人提出dual gate，利用增加閘極數目對通道有更好的控制能力來提升效能，卻沒有深入去探討閘極長度是否影響整個元件特性的發展。在這篇論文當中我們提出有效的多閘極之長度對通道的影響作為探討，此元件除了保持和傳統型的特性，只需要在傳統型閘極光罩部分做為修改。我們也會用ISE TCAD的模擬軟體去預期本次提出結構，將會有效的降低Drain端的電場使不理想效應得到有效的改善。次外本結構也不需要多光罩就可以預期的結果，無須增加成本之疑慮。
關鍵字: 雙閘極薄膜電晶體、多閘極、不理想效應

Polycrystalline silicon thin-film transistors (Poly-Si) are used widely in various field, such as active-matrix liquid crystal displays (AMLCDs), solar cell, active matrix organic light emitting diode (AMOLED) and flash memories because of their high mobility and driving current. In recent year, the device is promising candidate to be used in display system-on-panel (SOP) as memory and controller. Then the conventional poly – Si TFT is not enough in term of the speed and the current drive capability.
To increase the speed and the current of the poly-Si TFT, a double gate structure was proposed to provide an effective way to enhance the current drive capability of poly- Si TFT. Due to the double gate provides an additional current path. However the double gate is an attractive approach, there has the high electric field near the drain junction. It causes the device a larger leakage current and aggravates the kink effect than the convention structure. Then the light doped drain (LDD) combines the double gate. It has a effective way to improve the high electric field of double gate. Then the LDD also can reduce the leakage and maintain the high on-current. But the structure needs two the process of the expensive CMP.
In the past, the dual gate had reported. We know that the gate and the channel relationship. It has a good controlled to the channel and not confer the gate length. It this letter, we propose the dual gate length to effecting the device performance. We only need to change the gate mask. And my structure also effectively reduce the nonideal effect neat the drain junction. My structure requires an extra mask to increase the cost.
Keyword: DCTFT, dual gate, nonideal effect.

目錄
致謝………………………………………………………………………..
中文摘要…………………………………………………………………..
英文摘要…………………………………………………………………..
目錄………………………………………………………………………..
第一章 前言
1-1 薄膜電晶體簡介及應用………………………………………...
1-2 複晶矽薄膜電晶體之關鍵製造技術…………………………...
1-3 薄膜電晶體不理想效應………………………………………...
1-3.A 漏電流效應 ( Leakage current )………………………..
1-3.B 扭結效應 ( Kink Effect )……………………………….
1-3.C 熱載子效應 ( Hot Carrier Effect )……………………...
1-4 薄膜電晶體常見之結構………………………………………..
1-5 研究方向及目的………………………………………………..
1-6 研究概述………………………………………………………..
第二章 文獻回顧及結構設計……………………………………………
2-1 結構之文獻回顧………………………………………………..
2-1.A 雙閘極電晶體……………………………………………
2-1.B 多閘極電晶體……………………………………………
2-1.C Offset 結構…………………………………………………
2-1.D 新穎多閘極電晶體之設計………………………………...
第三章 新穎式多閘極電晶體之模擬分析………………………………
3-1前言………………………………………………………………..
3-2 模擬分析與驗證………………………………………………….
3-2.A 閘極長度變化影響………………………………………..
3-2.B閘極與閘極區間變化影響…………………………………
3-3.C 多閘極的長度變化影響…………………………………...
第四章 新穎式多閘極薄膜電晶體之實作結果…………………………
4-1 前言………………………………………………………………
4-2 實驗步驟…………………………………………………………
4-3 電性參數之萃取…………………………………………………
4-4 結果與討論……………………………………………………….
4-1.A新穎式多閘極薄膜電晶體之SEM圖………………………
第五章 結論………………………………………………………………
參考文獻…………………………………………………………………..




圖目錄
圖一 三種不理想效應…………………………………………………..9
圖二 漏電流效應機制…………………………………………………11
圖三 扭結效應…………………………………………………………13
圖四 扭結效應之寄生BJT…………………………………………….13
圖五 扭結電流…………………………………………………………13
圖六 熱載子效應………………………………………………………16
圖七 CHE機制…………………………………………………………17
圖八 DAHC機制………………………………………………………17
圖九 Offset 結構………………………………………………………18
圖十 LDD結構……………………………………...…………………19
圖十一 Air Cavity結構………………...………………………………19
圖十二 RSD結構………………………………………………………20
圖十三 FID結構………………………………….……………………21
圖十四 Double Gate Thin Film Transistor………………….…………24
圖十五 A New Multi-Channel Dual-Gate Poly-Si TFT Employing ELAR…………………………………………………………..25
圖十六A Novel Offset Gated Polysilicon Thin Film Transistor
Without an Additional Offset Mask …………………………..26
圖十七 新式多閘極電晶體……………………………...…………….27
圖十八 多閘極結構……………………………………………………29
圖十九 空乏區長度圖…………………………………………………30
圖二十 傳統TFT結構電位….…………………………………………31
圖二十一 雙閘結構(L1=5μm, L2=5μm)電位圖……………..………...32
圖二十二 雙閘結構(L1=8μm,L2=2μm)電位圖……………………….32
圖二十三 雙閘結構(L1=2μm,L2=8μm)電位圖……………………….32
圖二十四 傳統與雙閘極水平電位……………………………………33
圖二十五 傳統結構電場圖……………………………………………34
圖二十六 雙閘極結構(L1=5μm, L2=5μm)電場圖……………………34
圖二十七 雙閘極結構(L1=8μm, L2=2μm)電場圖……………………35
圖二十八 雙閘極結構(L1=2μm, L2=8μm)電場圖……………………35
圖二十九 傳統型與雙閘極水平電場圖………………………………36
圖三十 傳統型離子碰撞圖……………………………………………36
圖三十一 雙閘極結構(L1=5μm, L2=5μm)離子撞擊圖………………37
圖三十二 雙閘極結構(L1=8μm, L2=2μm)離子撞擊圖…….………...37
圖三十三 雙閘極結構(L1=2μm, L2=8μm)離子撞擊圖………………37
圖三十四 傳統型與雙閘極(L1=8μm, L2=2μm)電流圖………………38
圖三十五 閘極與閘極中間長度示意圖………………………………39
圖三十六 閘極與閘極中間長度1μm電位圖…………………………39
圖三十七 閘極與閘極中間長度2μm電位圖………………………...39
圖三十八 閘極與閘極中間長度3μm電位圖………………………...40
圖三十九 閘極與閘極間長度之水平電位……………………………40
圖四十 閘極與閘極之中間長度1μm電場圖………………………...41
圖四十一 閘極與閘極之中間長度2μm電場圖……………………...42
圖四十二 閘極與閘極之中間長度3μm……………………………...42
圖四十三 雙閘極水平電場圖…………………………………………43
圖四十四 中間長度( 1μm )離子撞擊圖……………………………..43
圖四十五 中間長度( 2μm )離子撞擊圖……………………………..44
圖四十六 中間長度( 3μm )離子撞擊圖……………………………..44
圖四十七 閘極長度(L1=2μm, L2=6μm, L3=2μm)之電位圖…….……45
圖四十八 閘極長度(L1=6μm, L2=2μm, L3=2μm)之電位圖……….…45
圖四十九 閘極長度(L1=L2= L3=L4=L5=2μm)之電位圖……………..46
圖五十 多閘極之水平電位圖…………………………………………46
圖五十一 閘極長度(L1=2μm, L2=6μm, L3=2μm)之電場圖…….……47
圖五十二 閘極長度(L1=6μm, L2=2μm, L3=2μm)之電場圖…….……47
圖五十三 閘極長度(L1=L2= L3=L4=L5=2μm)之電場圖…………..…47
圖五十四 三閘與多閘極水平電場圖…………………………………48
圖五十五 閘極長度(L1=2μm, L2=6μm, L3=2μm)之離子撞擊……….48
圖五十六 閘極長度(L1=6μm, L2=2μm, L3=2μm)之離子撞擊…….…49
圖五十七 閘極長度(L1=L2= L3=L4=L5=2μm)之離子撞擊……..……50
圖五十八 多閘極關鍵製程步驟………………………………………54
圖五十九 多閘極長度均為1μm的OM圖……………………………54
圖六十 閘長度( 8μm, 2μm, 2μm)的OM圖………………………...54
圖六十一 閘長度(2μm, 8μm, 2μm)的OM圖………………………55
圖六十二 雙閘閘長度(6μm, 4μm)的OM圖………….……………..55
圖六十三 雙閘極長度(9μm, 1μm)的OM圖………………………..55
圖六十四 傳統型薄膜電晶體SEM圖…………………………………60
圖六十五 傳統型薄膜電晶體電流圖…………………………………61
圖六十六 多閘極平均長度為1μm的SEM圖………………………...61
圖六十七 三閘極長度為(8μm, 1μm, 1μm)的SEM圖…………………62
圖六十八 傳統型薄膜電晶體電流圖…………………………………62
圖六十九 傳統型電流…………………………………………………62





表 目 錄
表1.1薄膜電晶體技術分類比較表……………………………………..4
表1.2各種複晶矽製作手法比較表…………………………………….8

公式
公式.1. TFT電流公式………….……………………………………30
公式.2. 臨界電壓萃取電流公式……………………………………58
公式.3. 次臨界區織T萃取公式……………………………………59
公式.4. 薄膜電晶體之電流公式……………………………………60
公式.5. 轉導係數公式………………………………………………60
公式.6. 電子遷移率公式……………………………………………60

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