臺灣博碩士論文加值系統

　　在大多數的系統單晶片(SoC)中會內嵌PLL當作時脈產生器，因其深植於晶片內部，因此很難使用外部的測試機直接測試它。對一個PLL產生的時脈訊號，最難量測的效能之一為訊號抖動(jitter)的量測。
　　
　　在本論文中，我們首先針對近年來應用於量測訊號抖動的內建自我測試技術進行分析探討，並歸納出各種方法的優點與可能面臨的挑戰。

　　其次，我們改良傳統上基於一個理想參考訊號來實現內建自我測試的方法，提出不需要理想參考訊號，僅以一個待測信號為輸入，結合統計分析的技巧，對於量測結果進行校正的測試技術，實驗結果顯示，經由校正所得到的結果有較佳的精確性。

　　最後，我們基於前述不需要理想參考訊號的測試方法，提出一個新穎的內建自我測試電路來量測訊號抖動，其包含兩個主要的子電路：抖動放大器與以環型振盪器為基礎的抖動統計電路。抖動放大器主要用來將微小的時間差異線性放大，以提高量測解析度；以環型振盪器為基礎的抖動統計電路用以建立訊號抖動的機率分佈長條圖(Histogram)，以便推算訊號抖動的大小。有別於傳統內建自我測試機制皆忽略內建自我測試電路本身也會產生多餘的抖動行為，在我們所提出的內建自我測試技術，利用不同線性放大倍率的技巧，加上簡單的統計分析與數學推估，可以有效的移除內建環型振盪器本身所產生多餘的訊號抖動，以得到更精確的量測結果。本論文所提出內建自我測試電路之主要功能區塊皆以TSMC 0.18 �慆製程進行模擬驗証，實驗結果顯示其可得到不錯的結果。

　Phase-locked loops (PLLs) are often served as clock generators and/or frequency synthesizers in a system on a chip (SoC). Since it is usually built inside the chip deeply, it is hard to test PLL directly by using automatic test equipments (ATEs). For a clock signal generated by a PLL, jitter is one of the specifications which are hardest to be test.

　At the beginning of this thesis, we survey and investigate several built-in self-test (BIST) schemes used for jitter measurement in recent years. We also summarize pros, cons and challenges in practical implementation for these BIST schemes.

　To accomplish the jitter measurement, it often needs a golden (jitter free) reference signal in many conventional BIST methods. However, it is hard to provide such ideal signal. Hence, we propose a BIST method which does not need an ideal reference clock. In this BIST method, we measure jitter and employ statistical analysis techniques to calibrate the measured data to achieve higher accuracy results.

　Besides, we propose a BIST circuit based on the method developed previously. The BIST circuit mainly contains two building blocks: jitter amplifier and ring oscillator based jitter calculating circuit. Jitter amplifier is used to linearly amplify tiny time intervals to enhance the measuring resolution. Ring oscillator based jitter calculating circuit is used to collect the timing data and build the histogram of jitter to estimate the amount of jitter. In contrast to conventional BIST methods, the proposed BIST scheme can remove the extra jitter generated by the built-in ring oscillator itself to obtain more accurate measuring results by using linear jitter amplifier and simple statistical techniques. All main function blocks proposed in this thesis are all verified and simulated with TSMC 0.18 �慆 process.

1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 ORGANIZATION OF THIS THESIS 2
THE REMAINDER OF THE THESIS IS ORGANIZED AS FOLLOWS: 2
2 BASICS FOR JITTER MEASUREMENT 4
2.1 CONCEPTS OF JITTER 4
2.1.1 Jitter and Phase Noise 5
2.1.2 Jitter Measurement 6
2.2 JITTER CLASSIFICATIONS 7
2.2.1 Classified by Properties 7
2.2.2 Classified by Measuring Time 8
2.3 JITTER BEHAVIORS FOR VCO AND PLL 10
2.3.1 Jitter Curves in Ring Oscillator 10
2.3.2 Jitter Curves in PLL 12
2.4 MODELING METHODS 14
2.4.1 Frequency Modulation 14
2.4.2 Periods with Random Jitter 16
3 PLL JITTER TESTING METHODS 18
3.1 ATE AND BIST 18
3.1.1 ATE Testing 19
3.1.1.1 Oscilloscope 19
3.1.1.2 BERT Testing 21
3.1.1.3 Bathtub Curves 21
3.1.2 BIST 23
3.2 CONSIDERATIONS FOR JITTER BIST 23
3.2.1 Decision Flow 23
3.2.2 Should we Combine PLL and BIST? 24
3.2.3 Less Loading Effect 26
3.2.3.1 Using the Accumulating Property 27
3.2.3.2 Self-Measurement 29
3.2.3.3 Other Considerations 33
3.3 SOME TECHNIQUES FOR JITTER BIST 33
3.3.1 Vernier Delay Line 33
3.3.2 Oscillators 35
3.3.3 Short Discussion for TDC 36
3.4 SOME CORRECTION OF CALCULATIONS 37
3.4.1 Questions 37
3.4.2 Assumptions: 39
3.4.3 The Derivation 39
3.4.4 The Result 40
3.4.5 The Example 41
4 DESIGNING A JITTER BIST 45
4.1 THE PROPOSED BIST 45
4.2 BLOCKS 46
4.2.1 Adjustable Delay 46
4.2.2 Edge Detector 47
4.2.3 Time Amplifier 47
4.2.4 The Ring Oscillator 51
4.2.5 Counter 51
4.2.6 Short Discussion for DFF 52
4.2.7 Analysis from the Statistical View 53
5 CONCLUSIONS AND FUTURE WORK 57
5.1 CONCLUSIONS 57
5.2 FUTURE WORK 58
REFERENCE 59
A CALCULATING JITTER WITH CDF 62
A.1 THE BASIC SETTING OF THE MEASUREMENT 62
A.2 THE STANDARD DEVIATION AND RMS VALUE 65
BIOGRAPHY 66

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