臺灣博碩士論文加值系統

加法器為一基本的算術元件，通常也是關鍵路徑的主要因素。漣波進位加法器的最大操作速度通常侷限於進位傳播延遲，且其傳播延遲將隨著位元數增加而變差。本篇論文使用動態電路技術來實現四種不同架構的快速漣波進位加法器，彽成本與高速度的特性讓其非常合適被應用在任何的資料運算單元。
我們使用32位元漣波加法器來證明所提出的各種動態漣波進位加法器。所有的設計與比較是基於TSMC 0.25um CMOS製程並且操作在2.5V。SPICE模擬結果發現，我們所提出的動態漣波進位加法器比傳統靜態漣波進位加法器快至少2.38倍之多。另一方面，相對於過去文獻中提出的動態連波進位加法器，我們的設計不論在速度、功率消耗與面積也都有較佳的表現。

Adders are fundamental building blocks and often constitute part of the critical path. The maximum operating speed of a Ripple Carry Adder (RCA) is limited by the carry propagation delay, and the penalty of the propagation delay depends on the number of primary input bits. In this paper, we propose four high-speed and compact ripple carry adder designs. The key techniques of these novel designs are race-free dynamic CMOS logic technique for high-speed and compact designs.
We demonstrate these designs approach using a 32-bit ripple carry adder built with the TSMC 0.25-um CMOS technology. The adder operates at 2.5V. The SPICE simulation shows that the proposed Dynamic Ripple Carry Adders (DRCAs) are at least 2.38 times faster than the conventional static ripple carry adder (SRCA). Further all of the proposed designs compare much favorably to the previous DRCA design that employs the DCVS logic.

目 錄
中文摘要 I
英文摘要 II
目 錄 III
圖目錄 V
表目錄 VI
第1章 緒 論 1
第2章 傳統式漣波進位加法器之設計 3
2-1 傳統式靜態漣波進位加法器 3
2-1.1 單一位元加法器設計 3
2-1.2 多位元連波進位加法器設計 6
2-1.3 設計觀念 8
2-2 傳統式動態漣波進位加法器 9
2-2.1 NP CMOS邏輯型式 9
2-2.2 DCVS邏輯型式 11
第3章 新型的動態漣波進位加法器設計 15
3-1 無競賽問題之NP CMOS邏輯漣波進位加法器 15
3-2 All-N動態漣波進位加法器(AN_DRCA) 16
3-3 正邏輯輸入之動態漣波進位加法器(PL_DRCA) 17
3-4 動態反相漣波進位加法器(DI_DRCA) 18
3-5 本章小結 19
第4章 實驗結果 21
4-1 簡介 21
4-2 佈局考量 23
4-3 Post-layout模擬 27
第5章 加法器之應用 30
5-1 簡介 30
5-2 2’s補數加減法器之設計觀念 30
5-3 Post-Layout模擬 34
第6章 結論與未來展望 41
6-1 結論 41
6-2 未來展望 43
參考文獻 44
附錄一 NP_DRCA之電路方塊圖與電晶體尺寸 46
附錄二 AN_DRCA之電路圖方塊與電晶體尺寸 47
附錄三 PL_DRCA之電路方塊圖與電晶體尺寸 48
附錄四 DI_DRCA之電路方塊圖與電晶體尺寸 49
圖 目 錄
圖2-1 單一位元加法器設計(32顆電晶體) 5
圖2-2 單一位元加法器設計(28顆電晶體) 6
圖2-3 多位元漣波進位加法器之設計 7
圖2-4 一位元動態加法器電路圖 10
圖2-5 NP CMOS動態漣波進位加法器與競賽問題 11
圖2-6 32位元動態漣波加法器使用DCVS邏輯 13
圖2-7 DCVS邏輯元件之電路圖 14
圖3-1 無競賽問題之NP CMOS動態漣波加法器 16
圖3-2 All-N CMOS動態漣波加法器 17
圖3-3 正邏輯輸入之動態蓮波加法器(PL_DRCA) 18
圖3-4 動態反相漣波進位加法器(DI_DRCA) 19
圖4-1 各種32位元動態漣波進位加法器之電路架構 23
圖4-2 各種32位元漣波進位加法器之floorplan與layout 26
圖4-3 產生最長路徑延遲之輸入狀態 27
圖4-4 各種RCA之最長路徑模擬波形 27
圖5-1 快速與低成本之16位元2’s補數加減法器 33
圖5-2 2’補數加減法器之管線式系統時序圖 34
圖5-3 2’s補數加減法器模組之電路圖 35
圖5-4 16-bit AN_DRCA之floorplan與layout 36
圖5-5 2’s補數加減法器模組之floorplan與layout 37
圖5-6 負緣觸發正反器之電路圖與佈局圖 39
圖5-7 2’s補數加減法器模組在管線式系統之floorplan與layout 39
圖5-8 post-layout模擬波形 40
表 目 錄
表2-1 加法器真值表 3
表4-1 各種32位元連波進位加法器 22
表4-2 post-layout模擬結果 28
表4-3 各種不同輸入狀態所產生的功率消耗(f=100MHz, Vdd=2.5V) 29
表5-1 2’s補數加減法器之真值表 32
表5-2 16-bit AN_DRCA之各種特色 36
表5-3 2’s補數加減法器之各種特色 37
表5-4 各種不同輸入狀態所產生的功率消耗(f=167MHz, Vdd=2.5V) 38
表5-5 2’s補數加減法器模組在管線式系統之各種特色 40
表5-6 各種不同輸入狀態所產生的功率消耗(f=189MHz, Vdd=2.5V) 40

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