臺灣博碩士論文加值系統

這篇論文針對多重缺陷的錯誤晶片提出一個考慮實體資訊並使用新穎辭典的診斷技術，我們的技術同時考慮錯誤遮蔽/增強效應以及拜占庭效應。我們使用影響單一缺陷有關的導線片段作為診斷的最小單位，然後，我們提出一個導線片段對應實體位置的技術來找出真正的缺陷。在ISCAS’89和ITC’99的電路上，多重導線開路缺陷的實驗顯示出我們診斷技術的能力。當插入的缺陷數量越多，此技術的診斷正確率會越高於商業軟體。當插入10個多重導線開入缺陷時，此技術的正確率(0.67)比商業軟體的正確率(0.31)還高出許多。

This thesis presents a physical-aware diagnosis technique for failing dies with multiple defects using novel dictionary. Our diagnosis technique considers fault masking/reinforcement and Byzantine effects simultaneously. We identify sections that involved in a defect as the smallest diagnosis unit. Then, we propose section to physical site mapping technique to find culprit defects. Simulations on ISCAS’89 and ITC’99 benchmark circuits with multiple open-via defects demonstrate the effectiveness of our diagnosis technique. The accuracy is higher than commercial tool when more defects are injected. The accuracy of MD-PhD with 10 open-via defects injected (0.67) is much higher than commercial tool (0.31).

1 Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Proposed Techniques 3
1.3 Contributions 5
1.4 Organization 6
2 Chapter 2 Background 7
2.1 Prior Work in Multiple Defect Diagnosis 7
2.2 SLAT Diagnosis 9
2.3 Path Tracing Technique 11
2.4 Failing Output Partitioning 15
2.5 Byzantine Effect 18
3 Chapter 3 Proposed Techniques 20
3.1 Overall Flow 20
3.2 Key Concept 22
3.2.1 Section 22
3.2.2 Section-based Fault Simulation 23
3.3 Compress Diagnosis Dictionary 27
3.4 SLIC Diagnosis [Chen 14] 29
3.4.1 Bottom-up Hierarchical Tree Construction 30
3.4.2 Top-down Cluster Partitioning 32
3.5 Defect Mapping 36
3.5.1 Suspect Seed Section 37
3.5.2 Section to Physical Site Mapping 39
4 Chapter 4 Experimental Results 41
4.1 Simulation Setup 41
4.2 Simulation Results 42
4.3 Dictionary Memory Requirement Analysis 44
Chapter 5 Conclusion and Future Work 46
5 References 48

[Abramovici 84]M. Abramovici, P.R. Menon, and D.T. Miller, “Critical Path Tracing: An Alternative to Fault Simulation,” IEEE Design & Test of Computers, Vol. 1, pp. 89-93, Feb. 1984.
[Acken 91]J. M. Acken and S. D. Millman, “Accurate modeling and simulation of birdging faults,” in Proc. of the Custom Integrated Circuits Conf, pp. 17.4.1-17.4.4, 1991.
[Acken 92]J.M. Acken; S.D. Millman, "Fault Model Evolution for Diagnosis: Accuracy vs Precision," in Custom Integrated Circuits Conference, pp.13.4.1, 13.4.4, 1992.
[Bartenstein 01]T. Bartenstein, D. Heaberlin, L. Huisman, and D. Sliwinski, “Diagnosing Combinational Logic Designs Using the Single Location At-a-time (SLAT) Paradigm,” in Proc. of Int’l Test Conf., pp. 287-296, 2001.
[Chen 14]P.-J. Chen, C.-C. Che, H. Jasmine Chao, James C.-M. Li, S.-F. Kuo, P.-Y. Hsueh, C.-Y. Kuo and J.-N. Lee, “Physical-aware Systematic Multiple Defect Diagnosis,” in IET Computers & Digital Techniques, 2014.
[Chen 15]J.-Y. Chen, James C.-M. Li, “Physical-aware Critical Path Tracing for Defect Diagnosis,” National Taiwan University, 2015.
[Huang 01]S. Y. Huang, “On Improving the Accuracy of Multiple Defect Diagnosis,” in Proc. of VLSI Test Symposium, pp. 34-39, 2001
[Huang 02]S. Y. Huang, “Diagnosis of Byzantine Open-Segment Faults,” in Proc. of the Asian Test Symposium, pp 248-253, 2002
[Huisman 04]L. M. Huisman, “Diagnosing Arbitrary Defects in Logic Designs using Single Location at a Time (SLAT),” in IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems, vol.23, no.1, pp.91-101, 2004.
[Jain 99]A. K. Jain, M. N. Murty and P. J. Flynn, “Data Clustering: a Review,” ACM Computer Surveys, vol 31, pp. 264-323, 1999.
[Lamport 82]L. Lamport, S. Robert, and P. Marshall. "The Byzantine Generals Problem." ACM Transactions on Programming Languages and Systems (TOPLAS) 4.3. pp. 382-401, 1982
[Lin 06]Y.-C. Lin and K.-T. Cheng, “Multiple-fault Diagnosis Based on Single-fault Activation and Single-output Observation,” in Proc. of Design Automation and Test in Europe, pp. 424-429, 2006.
[Lin 07]Y.-C. Lin, F. Lu, and K. T. Cheng, “Multiple-fault Diagnosis based on Adaptive Diagnostic Test Pattern Generation,” IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems, vol. 26, pp. 932-942, 2007.
[Mentor 09]“Mentor Graphics YieldAssist User Guide,” Mentor Graphics, 2009.
[Nangate 09]“Nangate 45nm Opec Cell Library,” http://www.nangate.com
[OpenAccess 11]http://www.si2.org/openeda.si2.org
[Pomeranz 04]I. Pomeranz, S. Venkataraman, S. M. Reddy, and B. Seshadri, “Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis,” in Proc. of Design, Automation and Test in Europe, pp. 68-73, 2004.
[Synopsys 08]“Synopsys Tetramax User Guide,” Synopsys, 2008.
[Takahashi 02]H. Takahashi, K. O. Boateng, K. K. Saluja and Y. Takamatsu, “On Diagnosing Multiple Stuck-at Faults Using Multiple and Single Fault Simulations in Combinational Circuits,” IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems, vol. 21, no. 4, pp. 362-368, 2002.
[Tang 10]X. Tang, W.-T. Cheng, R. Guo and S. M. Reddy, “Diagnosis of Multiple Physical Defects Using Logic Fault Models,” in Proc. of the Asian Test Symposium, pp. 94-99, 2010.
[Veneris 99]A. Veneris, S. Venkataraman, I.N. Hajj, W.K Fuchs, “Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits”, in Proc. of VLSI Test Symposium, pp. 58-63, 1999.
[Venkataraman 01]S. Venkataraman and S.B. Drummonds, “POIROT: Applications of a Logic Fault Diagnosis Tool,” IEEE Design & Test of Computers, pp. 19-30, 2001.
[Wang 03]Z. Wang, K.-H. Tsai, M. Marek-Sadowska, and J. Rajski, “An Efficient and Effective Methodology on the Multiple Fault Diagnosis,” in Proc. of Int. Test Conf., pp.329 -338 2003.
[Wang 06]T. Z.Wang, M. Marek-Sadowska, K-H Tsai, J. Rajski, “Analysis and Methodology for Multiple-Fault Diagnosis,” IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems, vol. 25, pp. 558-575, no. 3, 2006.
[Ye 10]J. Ye, Y. Hu, and X. Li, “Diagnosis of multiple arbitrary faults with mask and reinforcement effect,” in Proc. of Design, Automation & Test in Europe. pp. 885-890, 2010.
[Yu 08]X. Yu and R. D. Blanton, “An Effective and Flexible Multiple Defect Diagnosis Methodology Using Error Propagation Analysis,” in Proc. of Int’l Test Conference, pp. 977-987, 2008.
[Yu 10]X. Yu and R. D. Blanton, “Integrated Circuit Diagnosis of Circuits with Multiple Defects of Arbitrary Characteristics,” IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems, vol. 29, no. 6, pp. 977 - 987, June 2010.
[Zou 06]W. Zou, W. T. Cheng, S. M. Reddy, H. Tang, “On Methods to Improve Location Based Logic Diagnosis,” in Proc of VLSI Design, pp. 181-187, 2006.