臺灣博碩士論文加值系統

此論文提出新穎的積體電路架構為並行靜態二元及三元內容可定址記憶體，且採用低功率和高彈性的內容可定址記憶體架構。此架構克服缺點且具有單一位元線和雙位元線的優點。本論文所提出的低功率二元及三元內容可定址記憶體的配對線架構具備反及閘的低靜態消耗功率，虛擬N型金氧半電晶體的高速運算，以及互補式金氧半電晶體的低消耗功率和低成本。
本研究利用0.18 �慆製程實現128×32二元內容可定址記憶體，其HSPICE模擬結果顯示所提出的架構功率在1.8 V電壓供應和延遲時間2.02 ns下，消耗功率為3.94 mW。晶片模擬結果，虛擬互補式金氧半電晶體的128×32二元內容可定址記憶體在0.18 �慆製程技術下，提升了76％搜尋速度和降低65％消耗功率。
此外，也利用0.13 �慆製程技術實現64×128三元內容可定址記憶體，具有先進局部搜尋線控制，其HSPICE模擬結果顯示，在1.2 V電壓供應和延遲時間6.06 ns下，消耗功率為2.04 mW。所提出的三元內容可定址記憶體架構減少了26％的功率消耗和增進了23％的搜尋速度。

This thesis presents a novel VLSI architecture for fully parallel static type binary and ternary content addressable memories (BCAM and TCAM) with low power and high flexibility features by using novel CAM cell structures. The proposed CAM core cell structures eliminate the drawbacks and adapt the advantages of single bit line and dual bit line cell structures. In this work, the word match line (ML) structure of low power BCAM and TCAM adapts the proposed NAND based static pseudo CMOS (NPC) logic and static pseudo CMOS (PC) logic respectively which comprises the advantages of NAND structure such as low static power, pseudo NMOS logic such as high speed operation and CMOS logic such as low power and low cost. HSPICE simulations for 128×32 BCAM systems were performed with 0.18 �慆 technology and the result shows that the proposed design provides the power dissipation of 3.94 mW with the delay time of 2.02 ns under 1.8 V supply voltage. The measurement results of 128×32 PC-BCAM (under 0.18 �慆 CMOS technology) shows that the proposed BCAM cell reduces 76% of power dissipation and improves 65% of search speed. Further more, spice simulations were carried out for 64×128 TCAM systems with advanced local search line control (LSC) technique under 0.13 �慆 technology which shows that the proposed design gives the power dissipation of 2.04mw with the delay time of 6.06 ns under 1.2 V supply voltage. In 64×128 TCAM, proposed TCAM cell reduces 26% of power dissipation and improves about 23% of search speed.

Table of Contents

Table of Contents ...................................i
List of Figures......................................iv
List of Tables.......................................vi

Chapter 1 Introduction.................................1
1.1 Basic Idea of CAM..................................1
1.2 Motivation of the Work.............................3
1.3 Organization of the Thesis.........................6

Chapter 2 Low Power CMOS Logic and CAM Core Cells......7
2.1 CMOS Logic Design Styles...........................7
2.1.1 Static CMOS logic................................7
2.1.2 Pseudo NMOS logic...............................11
2.1.3 Dynamic logic...................................12
2.2 Basic Operation Principle of CAM .................16
2.3 Different Types of CAM Core Cells................17
2.3.1 NOR and NAND types of binary CAM core cells....18
2.3.2 Modified binary CAM core cells .................21
2.3.3 Single bit line CAM cell structures.............24
2.3.4 Ternary CAM core cells..........................25
2.4 Basic Idea of Matchline Structure.................26
2.4.1 Equivalent circuit model of match line and its delay ............................................ 26
2.4.2 Applications of CAM.............................27

Chapter 3 Low Power Design Solutions and Word Matchline Techniques............................................29
3.1 Matchlines and Searchlines with CAM cell Array....30
3.1.1 NOR type word line structure....................30
3.1.2 NAND type word line structure...................31
3.1.3 NAND-NOR type word line structure...............32
3.1.4 Charge injection and current saving based word line structure .............................................33
3.1.5 PB based pseudo NMOS type word line structure...35
3.1.6 AND type word line structure....................36
3.2 Low Power Design Solutions........................37
3.2.1 Low swing technique.............................38
3.2.2 Current race technique..........................39
3.2.3 Selective precharge technique...................40
3.2.4 Pipe lined technique............................41
3.2.5 Current saving control (CSC) technique..........42

Chapter 4 Proposed Binary and Ternary CAM Cell Structures with NPC Wordline Structure...........................43
4.1 Proposed CAM Cells Structure......................44
4.1.1 Entire CAM system...............................44
4.1.2 Proposed BCAM cells.............................45
4.1.3 Proposed TCAM cells.............................49
4.1.4 BCAM and TCAM cells - Transistors sizing........51
4.2 Matchline Sensing Scheme..........................52
4.2.1 Pseudo CMOS (PC) logic..........................53
4.2.2 Proposed NAND based PC logic (NPC) structure....55
4.3 Searchline Control Technique......................57
4.3.1 Local Search line Control (LSC) logic...........57
4.4 Simulation Results................................61
4.4.1 Simulation results at different pValue..........62
4.4.2 Simulation results for Power-Performance – 32×32 binary CAM............................................63
4.4.3 Simulation results for Power-Performance – 128×32 binary CAM............................................65
4.4.4 Simulation results for Power-Performance – 64×128 ternary CAM...........................................67
4.4.5 Functionality verification......................69
4.4.6 Critical speed / delay measurement..............70
4.4.7 Summary and comparison of the reported designs..73
4.5 Discussions.......................................74
Chapter 5 Conclusions and Future Work.................75
5.1 Conclusions.......................................75
5.3 Future directions.................................77

References............................................78

Publications and Award................................84

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