臺灣博碩士論文加值系統

全球人口老化的趨勢愈來越嚴重，而老年人需要較完善的健康照顧，因此，如何建立健全的醫療照護就顯得格外重要。大部分的老年人卻深受慢性疾病所苦，由於慢性疾病必須長期的監控與治療，甚至耗費大量的醫療資源。因此，醫療植入通訊服務已逐漸形成一個新興的市場，預估可帶來龐大的商機。醫療植入通訊服務系統可以隨時隨地監測病人的生理資訊。其監測設備必須具有可植入式性以及短距離無線傳輸之功能。因此，短距離和低功率消耗成為設計接收機的重要課題。為達成上述目標，本篇論文提出兩種不同接收機之架構，全部晶片皆設計及實現於標準之0.18微米CMOS製程。
首先，第一顆晶片是一顆低功率可植入式生醫頻段頻率鍵移接收機。射頻輸入訊號先經由窄頻的低雜訊放大器來放大。之後經由混頻器降頻到中頻頻段再由中頻放大器放大中頻訊號到軌對軌。最後，經由特殊的低功率解調器解調出發射機發射的資料。
第二顆晶片是一個使用功率偵測技術之可變增益植入式低功率生醫頻段接收機。而功率偵測器是採用分貝的線性輸出架構來實現。接收機可以經由功率偵測器以及二位元快閃類比數位轉換器偵測輸入訊號的強度來控制中頻放大器的增益。如此一來，接收機可以藉由降低中頻放大器的增益來節省功率消耗。

The world is facing a floridisation problem. The old need better health care. Therefore, how to establish a pluperfect medical treatment and healthcare is especially important. Most of the senior citizens suffer from chronic diseases, which should be monitored and observed for a long term. Therefore, Medical Implant Communication Service (MICS) becomes a newly developing market. By using a Medical Implant Communication Service system, the patient’s vital signals can be measured at any time any place, so the measuring devices should be implantable and possess the ability of short-range wireless communication. As a result, short range and low power dissipation are important issues to the receiver. For these specifications, two kinds of receivers are proposed in this dissertation. All chips are implemented and fabricated in standard0.18-um CMOS process in the thesis.
The first chip is a low power implantable FSK receiver for Medical Implant Communication Service (MICS). A narrow-bandwidth low noise amplifier is used to amplify the input RF signal. And then, the mixer downconverts the radio frequency signal (RF) to intermediate frequency (IF). The intermediate frequency signal is amplified by an IF amplifier which enables the intermediate frequency signal to reach rail-to-rail. Finally, by using a remarkable FSK demodulator which has low power consumption, the transmitted data can be demodulated.
The second chip is a low power MICS band FSK receiver with power detection technique for implantable devices. The proposed linear-in-decibel output is employed for power detector topology. With a power detector and a 2-bit flash ADC, the receiver can detect the input signal strength, thereby controlling the gain of the IF amplifier. By lowering the gain, the receiver can save more power and extend the battery life.

摘要 I
Abstract III
Table of Contents V
List of Figures IX
List of Tables XV

Chapter 1 1
1.1 Motivation 1
1.2 Thesis Organization 3
Chapter 2 5
2.1 Introduction 5
2.2 Heterodyne Receiver 6
2.3 Homodyne Receivers 11
2.4 Image-Rejection Receiver: Hartley and Weaver 17
2.5 Digital-IF Receiver 21
2.6 Subsampling Receiver 22
2.7 Summary 25
Chapter 3 27
3.1 introduction 27
3.2 FSK modulation 28
3.3 System Architecture 29
3.4 Receiver implementation 33
3.4.1 Low Noise Amplifier 33
3.4.2 Mixer 38
3.4.3 IF Amplifier 47
3.4.4 Demodulator 51
3.5 Simulation and Measurement Result 59
3.5.1 Simulation 59
3.5.2 Measurement 62
3.6Summary 68
Chapter 4 71
4.1 introduction 71
4.2 System Architecture 72
4.3 Receiver implementation 73
4.3.1 Low Noise Amplifier 73
4.3.2 Mixer 73
4.3.3 IF amplifier 74
4.3.4 Gain control unit 74
4.3.4.1 Power detector 74
4.3.4.2 Flash ADC and digital process 83
4.3.5 Demodulator 85
4.4 Simulation and Measurement Result 87
4.4.1 Simulation 87
4.4.2 Measurement 91
4.6 Summary 100
Chapter 5 103
Reference 107

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