臺灣博碩士論文加值系統

在本論文中我們提出一個結合可組態仲裁演算法與Cross-Bar Switch的可規劃仲裁器設計，以達到一個具有公平及快速的仲裁及可彈性的調整頻寬的仲裁器，以提升系統整體的效能。並可很容易的整合於任何的On-Chip-Bus中應用，如AMBA。這個設計是先以軟體作仲裁效能分析，再以Verilog HDL作硬體實現並已於Altera Max+plus II 模擬成功，於ALTERA ACEX EP10K100ARC240之 FPGA作驗證及AMBA University Kit(AUK)作相容性驗證。

In order to obtain high bandwidth utilization and low latency for on-chip bus communication, a hybrid arbitration algorithm and a programmable arbiter architecture are described in this thesis. The hybrid arbitration algorithm contains static fixed priority algorithm in conjunction with dynamic algorithm to gain low latency in system performance is explained. The implementation of a programmable arbiter to increase the bandwidth utilization is proposed. The analysis of various combinations of the arbitration algorithms indicates a better performance can be achieved as compared with the traditional arbitration assignment scheme. The simulation results of the programmable arbiter are shown on Altera Max Plus II design environment and implementation in Altera EPF10K100ARC240-1 FPGA and verified in ARM AMBA University Kit (AUK) environment.

中文摘要………………………………………………………………………I
英文摘要…………………………….………………………………………II
誌謝…………………………………………………………………………III
目錄……………………………….…………………………………………IV
圖目錄…………………………………………………………………………V
表目錄………………….……………………………………………………VI
第一章 序論…………………………………………………………………1
1-1 研究動機與背景…………………………………………………………1
1-2 系統單晶片(System on Chip ；SoC)之發展概況……………………5
1-3 論文內容摘要……………………………………………………………9
第二章 系統晶片匯流排介紹…………………………………………….10
2-1 AMBA(Advanced Microcontroller Bus Architecture)基本介紹..11
2-2 AHB (Advanced High-performance Bus) ……………….…………13
2-3 APB (Advanced Peripheral Bus) ………………………………….21
第三章 系統晶片匯流排仲裁演算法…………………………………….23
3-1 匯流排仲裁演算法簡介……………………………………………….23
3-2 靜態仲裁演算法……………………………………………………….23
3-3 動態仲裁演算法……………………………………………………….24
3-3-1 Round-Robin 仲裁演算法………………………………………….24
3-3-2 FCFS(First-Come First-Serviced) 仲裁演算法………….....24
3-3-3 Lottery Bus仲裁演算法…………………………………………..25
3-4 動靜態混合仲裁演算法(Hybrid Arbitration Algorithm) …....26
第四章 可規劃仲裁器(Programmable Arbiter)之設計 ………………30
4-1 可規劃仲裁器系統架構……………………………………….......33
4-1-1 可規劃仲裁器整體仲裁流程…………….…………………………40
4-1-2 單匯流排操作模式………………………………………………….42
4-1-3 雙匯流排操作模式………………..……………………………….43
4-2 動靜態混合仲裁演算法(Hybrid Arbitration Block)架構……...45
4-2-1 仲裁演算法選擇模組架…………………………………………….49
4-2-2 Fixed-Priority架構……………………………………………….53
4-2-3 Round-Robin架構…………………………………………………..54
4-2-4 FCFS架構……….…………………………………………………..55
4-3 匯流排工作模式選擇模組架構……………………………………….57
4-3-1 Bus State Recorder 模組架構…….…………………………….57
4-3-2 Bus_1及Bus_2 Decoder 模組架構……….……………………….61
4-3-3 Per-Grant Decoder 模組架構…….…………………………....64
4-3-4 Dual-Bus Switch 模組架構……………………………………...65
第五章 可規劃仲裁器之硬體設計及驗證………………………………67
5-1 系統效能分析….………………………………………………………67
5-2 硬體描述語言設計及模擬….…………………………………………69
5-2-1 Hybrid Arbitration Block之設計及模擬…….…………………69
5-2-2 Bus State Recorder 模組之設計及模擬…………………………78
5-2-3 Bus_1及Bus_2 Decoder 模組之設計及模擬……………………..81
5-2-4 Per-Grant Decoder 模組之設計及模擬………………………….83
5-2-5 Dual-Bus Switch 模組之設計及模擬…….………………………85
5-2-6 Programmable Arbiter之整合設計及模擬……………………….91
5-3 FPGA 驗證................................................97
5-4 AUK(AMBA University Kit)應用實例........................100
第六章 結論與未來發展.....................................106
參考文獻….……………………………………………………………….108

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