臺灣博碩士論文加值系統

運算轉導放大器-電容 (OTA-C) 技術在高頻電路中已成為不可或缺的技術.但是,與其他類比電路一樣,運算轉導放大器-電容電路的測試是一項非常艱難的問題.在最近幾年, 這問題已愈來愈嚴重因為電路的複雜度已相對的增加.
在本論文中, 我們提出了一系統式的設計可測性的運算轉導放大器-電容電路.首先推導出運算轉導放大器-電容低通濾波器的狀態方程式之通式,同時介紹一些運算轉導放大器-電容震盪器的設計.然後會介紹一運算轉導放大器-電容電路的電流模式測試架構.根據此架構,我們提出了設計運算轉導放大器-電容電路之易測性設計的步驟.利用此步驟,我們可以很簡單且很快地將測試電路加到運算轉導放大器-電容電路上去.此方法的基本概念如下所述.比較從待測電路中取得之電流與從待測電路中之電壓經轉換而成的電流,那麼待測電路中功能不正常的元件就會有效率地同步偵測出來.此外,我們也提出了以不同的轉導值來設計可測性的運算轉導放大器-電容電路,同時也探討了電路中臨界值之取決.最後,會有一些模擬及實驗結果.本論文中, 我們用了0.5微米,2P2M的CMOS製程來製作一晶片.此晶片之實驗結果顯示我們的設計具有下列的優點: 1) 易於設計與實現; 2) 高準確度之錯誤偵測; 3) 對待測電路之影響不大; 4) 高速率 (同步) 偵錯; 5) 面積需求小.

The operational transconductance amplifier-capacitor (OTA-C) technique has become today the technique of choice for high-frequency circuits. However, similar to other analog circuits, testing an OTA-C based circuit is a difficult problem. In recent years, this problem becomes even more
difficult because of the increase of circuit complexity.
In this thesis, a systematic approach to design testable OTA-C based circuits is proposed. We first derive a general form for the state equation of OTA-C low-pass filters and OTA-C oscillators. Then, we present a general current-mode testable architecture for OTA-C based circuits. A universal procedure for the testable OTA-C based circuits design based on this
architecture is given. By using this procedure, we can easily and fastly add the test circuit to the OTA-C based circuits. The basic idea of this method is as follows. By comparing the current consumed by the circuit under test (CUT) and the current converted from the voltage levels of the CUT, abnormal function of circuit components can be concurrently and
efficiently detected. Besides, the testable OTA-C based circuits designed with multiple $g_m$ values are also proposed and the threshold determination is also discussed in this thesis. Finally, the simulation and experimental results are given. A test chip has been fabricated using a 0.5$\mu$m, 2P2M
CMOS technology. These results show that our design has the following advantages: 1) easy to design and implement; 2) high accuracy in error detection; 3) little impact on the circuit performance of the CUT; 4) high (concurrent) error detection speed; 5) small area overhead.

Chapter 1 Introduction 1
Chapter 2 Design of OTA-C based Circuits 6
Chapter 3 Testable design of OTA-C based Circuits 25
Chapter 4 Multiple gm Values and Threshold Determination 39
Chapter 5 Simulation Results 47
Chapter 6 Test Chip 56
Chapter 7 Conclusions 67

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