臺灣博碩士論文加值系統

隨著資料傳輸速率的急速演進，在無線網路基頻段整合具有寬頻寬的類比積體電路方塊將會是一個不可抵抗的未來潮流。另一方面，一個可以應用於多重標準接收機（Multi-Standard Receiver）的單一電路方塊對於加強行動電話的使用度來說是一個相當經濟的實現方式。這篇論文中所提出之應用於多重標準接收機的金氧半（CMOS）可變增益放大器（VGA）就是希望能滿足上述的這兩項趨勢。
一般來說，可變增益放大器是由一個自動增益控制迴路（AGC Loop）所控制。隨著資料傳輸速率的增加，自動增益控制迴路用來作自動增益控制的時間區帶佔一個資料框架（Data Slot）的時間越來越短。為了確保資料傳輸的正確性，一個快速的自動增益穩定（Gain Settling）變得越來越重要。自動增益控制迴路的效能除了需要快速的增益穩定之外，精準的增益穩定，平穩（Stable）的增益
穩定，和低失真的訊號輸出都是重要的效能依據。在這篇論文中，我們建立了一個線性的自動增益控制迴路，並將迴路內可變增益放大器的效能以提出的可變增益放大器效能來取代，然後加以模擬，以了解迴路的動態表現。
另外，在這篇論文中，將針對所提出的一個應用於多重標準接收機的金氧半可變增益放大器作分析、設計、模擬，並以台積電0.18μm 1P6M CMOS 製程技術來加以實作。提出的可變增益放大器的輸出訊號可以維持固定的訊號大小及固定的群延遲（Group Delay）。其頻寬可以由GSM 的100KHz，WCDMA 的2MHz，延伸到WLAN 的10MHz，並且透過設計其頻寬為可調（Adjustable）來增加整體架
構雜訊和線性度的表現。這個可變增益放大器的增益可以由-10dB 變化到20dB，並且其增益變化時，頻寬可以維持一定的特性使得基頻數位訊號處理（DSP）電路得以簡化。此可變增益放大器採用1.8V 的電源供應，整體的功率消耗是2.43mW。晶片的面積是0.645x0.465mm。

With the rapid growth of higher data rate, integrating the analog circuit block with wide bandwidth in the baseband will be an indispensable trend in the future. On the other hand, a single circuit block which can be used for multi-standard receiver is an economic implementation
way to enhance the usability of the cell phone. A CMOS variable gain amplifier (VGA) for multi-standard receiver described in this thesis aims to meet these two demands.
In general, VGA is controlled by an automatic gain control (AGC) loop. As the data rate increases, the data slot which is used for the AGC loop to settle is getting smaller. A fast gain settling of the AGC loop becomes more and more important to make sure the data transfer is correct. The performance of the AGC loop can be characterized not only by a fast gain settling, but also the precise gain settling, the stable gain settling, and a low-distortion output signal. Alinear model of the AGC loop is set up and simulated with the performance of VGA modeled as the proposed one to see the dynamics of the loop.
In this thesis, a proposed VGA for the multi-standard receiver is analyzed, designed, and implemented using the standard 0.18um 1P6M CMOS technology. The output signal of the VGA can be of constant signal level and contant group delay. The bandwidth of the VGA is extended from GSM 100KHz, WCDMA 2MHz to WLAN 10MHz, and designed to be adjustable for the noise and linearity concern of the total architecture. The gain of tha VGA ranges from -10dB to
20dB, and the constant bandwidth peroperty with different gain settings helps the simplification of DSP circuitry in the baseband. The total power consumption of the VGA is 2.43mW at 1.8V supply voltage. The chip area is 0.645mm x 0.465mm.

[1] R. Harjani, ”A low-power CMOS VGA for 50 Mb/s disk drive read channels,” IEEE Trans. Circuits and Systems, Part II, vol. 42, pp. 370-376, Jun. 1995.
[2] W. A. Serdijn, A. C. van derWoerd, J. Davidse, and A. H. M. Van Roermund, ”A low-voltage low-power fully integratable automatic gain control for hearing instruments,” IEEE Journal of Solid-State Circuits, vol. 29, pp.943-946, Aug. 1994.
[3] G. S. Sahota and C. J. Persico, ”High dynamic range variable-gain amplifier for CDMA wireless applications,” in ISSCC’97, San Francisco, CA, 1997, pp. 374-375. Session 22, paper 22.6.
[4] P.C. Huang, ”An automatic gain control architecture for SONET OC-3 VLSI” IEEE Trans. on Circuits and Systems, Part II, vol. 44, pp. 779-783, Sep. 1997.
[5] M. Shiue, C. C.Wangc, and W.Way, ”A VLSI design of dual-loop automatic gain control for dual-mode QAM/VSB CATV modem,” Proc. IEEE Int. Symposium Circuits and Systems,
Monterey, CA, 1998.
[6] Toshio Fujisawa et al, ”A Single-Chip 802.11a MAC/PHY With a 32-b RISC Processor”IEEE Journal of Solid-State Circuits, vol. 38, pp.2001-2009, Nov. 2003
[7] Wolfram Kluge et al, ”A 2.4GHz CMOS Transceiver for 802.11b Wireless LANs” in ISSCC’03, pp. 360-361. Session 20, paper 20.6.
[8] Hiroki Ishikuro et al, ”A Single-Chip CMOS Bluetooth Transceiver with 1.5MHz IF and Direct Modulation Transmitter” in ISSCC’03, pp. 94-95. Session 5, paper 5.5.
[9] Willy Hioe et al, ”0.18um CMOS Bluetooth Analog Receiver With 88-dBm Sensitivity”, IEEE Journal of Solid-State Circuits, vol. 39, pp.374-377, Feb. 2004
[10] Y.S. Youn et al, ”1GHz-band Low Distortion Up-converter with a Linear in dB Control VGA for Digital TV Tuner,” IEEE Radio Frequency Integrated Circuits Symposium, 2001.
[11] F. Behbahani, A. Abidi et al, ”Adaptive Analog IF Signal Processor for a Wide-Band CMOS Wireless Receiver,’ IEEE Journal of Solid-State Circuits, vol. 36, no. 8, pp. 1205-1216, August
2001.
[12] B. Celvo, S. Celma, M.T. Sanz, ”High-Frequency digitally programmable gain amplifier,”Electronic Letters, vol.39, no. 15, July, 2003.
[13] Y.S. Youn et al, ”A CMOS IF Transceiver with 90dB Linear Control VGA for IMT-2000 Application,” Symposium on VLSI Circuits Digest of Technical Papers, 2003.
[14] T. Maruyama et al, ”Single-Chip IF Transceiver IC withWide Dynamic Range Variable Gain Amplifiers forWideband CDMA Applications,” Symposium on VLSI Circuits Digest of Technical Papers, March 2001.
[15] U. Dasgupta et al, ”Transmit/Receive IF Chip Set for WCDMA Mobiles in 0.35-um CM/OS,”IEEE Trans. on Microwave Theory and Techniques, vol. 50, no. 11, Nov. 2002.
[16] O.Watanabe et al, ”A 380-MHz CMOS Linear-in-dB Signal-summing Variable Gain Amplifier with Gain Compensation Techniques for CDMA Systems,” Symposium on VLSI Circuits
Digest of Technical Papers, 2002.
[17] O. Watanabe, S. Otaka, M. Ashida, and T. Itakura, ” A 380-MHz CMOS linear-in-dB signalsumming variable gain amplifier with gain compensation techniques for CDMA systems,”Symposium on VLSI Circuits Digest of Technical Papers, 2002, pp. 136-139.
[18] Paolo Orsatti, Francesco Piazza, and Quiating Huang, ”A 71-MHz CMOS IF-Baseband Strip for GSM,” IEEE Journal of Solid State Circuits, vol. 31, pp.104-108, Jan. 2000.
[19] C.C. Hsu, J.T. Wu, ”A Highly Linear 125-MHz CMOS Switched Resistor Programmable Gain Amplifier,” IEEE Journal of Solid State Circuits, vol. 38, no. 10, pp. 1663-1670, Oct. 2003.
[20] Hassan O. Elwan, Ahmed M. Soliman, and M. Ismail, ”Digitally Programmable Decibel-Linear CMOS VGA for Low-Power Mixed-Signal Applications,” IEEE Trans. Circuits and
Systems, Part II, vol. 47, no. 5, pp. 245-254, May 2000.
[21] Hassan Elwan, Ahmed M. Soliman, and M. Ismail,”A CMOS Norton Amplifier-Based Digitally Controlled VGA for Low-Power Wireless Applications,” IEEE Trans. Circuits and Systems, Part II, vol. 48, no. 3, pp. 388-398, March 2001.
[22] J. Guido et al, ”Analog front end IC for category I and II ADSL,” Symposium on VLSI Circuits Digest of Technical Papers, 2000, pp. 178-181.
[23] J. M. Khoury, ”On the design of constant settling time AGC circuits,” IEEE Trans. Circuits and Systems, Part II, vol. 45, pp. 283-294, March 1998.