臺灣博碩士論文加值系統

本論文提出利用0.18μm CMOS製程實現一12位元超低耗能連續近似式類比數位轉換器，此類比數位轉換器使用具備消除過偏移量功能的前置放大器來降低比較器的偏移量，並且使用capacitor splitting DAC來減少DAC的誤差量及功率消耗。為了得到更好訊號雜訊比值，我們使用一個具有軌對軌(Rail-to-rail)輸入範圍的放大器來作為前置放大器的第一級，使類比數位轉換器可以接受軌對軌的輸入訊號。為了讓前置放大器在低電壓下亦能正常工作，我們並聯主動式正電阻和主動式負電阻來作為其負載，使其在0.5V之下仍可正常工作。量測結果顯示，當使用供應電壓為0.55伏特且輸出頻率為1KS/s時，此連續近似式類比數位轉換器可提供軌對軌的輸入範圍，以及50.73dB的訊號對雜訊諧波比(SNDR)，且此類比數位轉換器之功率消耗只有35nW，而其有效解析度頻寬可以到達奈奎斯(Nyquist)頻寬(500Hz)，此時相對應之能源FOM (Figure of merit)可達124fJ/conversion-step，與已知文獻中功耗最低之類比數位轉換器相較，此類比數位轉換器消耗功率僅為其24分之一，為目前已知消耗功率最低的類比數位轉換器。

This paper presents a 12-bit, ultra low power successive approximation analog-to-digital converter in TSMC 0.18μm 1P6M CMOS process. The analog-to-digital converter uses the offset-free pre-amplifiers to alleviate the impacts of the comparator’s offset. The bridging capacitive DAC is adopted to reduce the nonlinearity and to save the power of the DAC. The pre-amplifiers with a rail-to-rail input range are used to make the input range of the ADC also rail-to-rail. We used a diode-connected transistor in parallel with a negative resistor as the loads of the pre-amplifers in order to enable them operating at a supply voltage as low as 0.5V. Measurement results show that at an output rate of 1KS/s and a supply voltage 0.55V, the SA ADC provides a rail-to-rail input range and achieves a signal-to-noise-distortion ratio (SNDR) of 50.7dB and an effective resolution bandwidth (ERBW) up to the Nyquist bandwidth (500Hz). Its power consumption is as low as 35 nW, corresponding to an energy figure of merit (FOM) as good as 124fJ/conversion-step. The power of the proposed ADC is 24 times better than the lowest record of the state-of-the-art works as far as we know.

中文摘要 I
英文摘要 II
誌謝 IV
目錄 V
圖目錄 VIII
表目錄 XI
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機與目的 1
1.3 論文章節組織及研究方法 4
第二章 ADC介紹 5
2.1 Sigma-delta類比數位轉換器 5
2.2 積分式類比數位轉換器(Integrating ADC) 6
2.3 連續漸近式類比數位轉換器(SA ADC) 8
2.4 循環式類比數位轉換器(Cyclic ADC) 9
2.5 類比數位轉換器之選擇 10
第三章 十二位元超低功率連續漸近式類比數位轉換器設計 12
3.1 提出之SA ADC 13
3.1.1 取樣保持電路(Sample and hold, S/H) 15
3.1.2 數位類比轉換器(DAC) 22
3.1.3 比較器(Comparator) 29
3.1.3.1 前置放大器 (Pre-amplifier) 31
3.1.3.2 比較器 (Comparator)[4] 37
3.1.4 連續近似暫存器(SAR) 37
3.2 ADC佈局圖 39
第四章 模擬與驗證 41
4.1 供應電壓為1V之模擬結果 41
4.1.1 動態參數 41
4.1.2 功率消耗(Power dissipation) 43
4.2 供應電壓為0.9V之模擬結果 45
4.2.1 動態參數 45
4.2.2 功率消耗(Power dissipation) 47
4.3 供應電壓為0.55V之模擬結果 49
4.4 供應電壓為0.5V之模擬結果 52
4.5 ADC模擬結果與比較 53
第五章 量測結果 56
5.1 量測環境設定 56
5.2 供應電壓為0.55V之量測結果 57
5.2.1 動態參數 57
5.2.2 靜態參數 61
5.2.3 功率消耗 62
5.3 供應電壓為0.5V之量測結果 63
5.3.1 動態參數 63
5.3.2 靜態參數 65
5.4 供應電壓為0.9V之量測結果 66
5.4.1 時脈頻率490KHz 66
5.4.1.1 動態參數 66
5.4.1.2 靜態參數 70
5.4.2 時脈頻率210KHz 71
5.4.2.1 動態參數 71
5.4.2.2 靜態參數 75
5.4.3 功率消耗 76
5.5 供應電壓為1V之量測結果 78
5.5.1 動態參數 78
5.5.2 靜態參數 80
5.5.3 功率消耗 82
5.6 效能分析 82
5.7 量測結果與比較 84
第六章 結論與未來展望 87
附錄 A 88
附錄 B 95
參考文獻 97

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